Alternatives and similar repositories for riscv-torture:

Users that are interested in riscv-torture are comparing it to the libraries listed below

• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated last month
• riscv-ovpsim / imperas-riscv-tests
  ☆166Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 6 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆170Updated last month
• ucb-bar / berkeley-hardfloat
  ☆301Updated 4 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆163Updated 5 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆257Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆120Updated 3 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆180Updated 2 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆240Updated 3 weeks ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆182Updated last month
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆229Updated 4 months ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆128Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆143Updated 2 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆169Updated 6 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆236Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆146Updated 2 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆148Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆101Updated 2 years ago
• SpinalHDL / NaxRiscv
  ☆270Updated last month
• chipsalliance / VeeR-ISS
  ☆127Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆155Updated this week
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆241Updated 2 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆101Updated 3 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 2 months ago