riscv / riscv-j-extensionLinks
Working Draft of the RISC-V J Extension Specification
☆190Updated 2 months ago
Alternatives and similar repositories for riscv-j-extension
Users that are interested in riscv-j-extension are comparing it to the libraries listed below
Sorting:
- ☆149Updated last year
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆152Updated last week
- Simple demonstration of using the RISC-V Vector extension☆46Updated last year
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- RISC-V Architecture Profiles☆160Updated 5 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆214Updated last year
- The SiFive wake build tool☆91Updated this week
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆90Updated last week
- Machine-readable database of the RISC-V specification, and tools to generate various views☆90Updated this week
- QEMU with support for CHERI☆59Updated last month
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆221Updated last year
- RISC-V Processor Trace Specification☆191Updated last month
- RISC-V IOMMU Specification☆125Updated last week
- ☆281Updated this week
- Documentation of the RISC-V C API☆77Updated last week
- RISC-V Packed SIMD Extension☆150Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 8 months ago
- RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC☆99Updated 3 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆272Updated last week
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆74Updated this week
- Rust RISC-V Virtual Machine☆106Updated 8 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- Fork of LLVM adding CHERI support☆56Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆173Updated this week
- ☆30Updated last week
- ☆89Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- ☆92Updated 4 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆147Updated 9 months ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆110Updated 2 weeks ago