Alternatives and similar repositories for riscv-j-extension

Users that are interested in riscv-j-extension are comparing it to the libraries listed below

• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• sifiveinc / wake
  The SiFive wake build tool
  ☆91Updated this week
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Updated last year
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆88Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆198Updated 2 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆168Updated last week
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆93Updated this week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆153Updated last month
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆283Updated this week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆63Updated 4 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 5 months ago
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆82Updated last week
• riscv-software-src / riscv-unified-db
  Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools
  ☆122Updated last week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆144Updated last week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆236Updated last year
• embench / embench-iot
  The main Embench repository
  ☆298Updated last year
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆111Updated 4 months ago
• chipsalliance / t1
  ☆304Updated this week
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆78Updated last week
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆222Updated last year
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆49Updated last year
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆227Updated 2 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆205Updated this week
• riscv / riscv-aia
  ☆98Updated 3 months ago
• fwsGonzo / bigassm
  Assemble 128-bit RISC-V
  ☆46Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆180Updated 7 months ago