riscv / riscv-j-extension
Working Draft of the RISC-V J Extension Specification
☆169Updated last month
Related projects ⓘ
Alternatives and complementary repositories for riscv-j-extension
- ☆150Updated 8 months ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆145Updated this week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆146Updated 2 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆85Updated 2 weeks ago
- The SiFive wake build tool☆86Updated this week
- Working draft of the proposed RISC-V Bitmanipulation extension☆204Updated 8 months ago
- Bare Metal Compatibility Library for the Freedom Platform☆155Updated 11 months ago
- Rust RISC-V Virtual Machine☆88Updated 2 weeks ago
- RISC-V Processor Trace Specification☆164Updated last week
- RISC-V Architecture Profiles☆119Updated 3 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆217Updated this week
- RISC-V Packed SIMD Extension☆141Updated last year
- Documentation of the RISC-V C API☆75Updated last week
- RISC-V IOMMU Specification☆94Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆150Updated 2 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆218Updated 11 months ago
- ☆81Updated 2 years ago
- ☆81Updated this week
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆247Updated last week
- RISC-V architecture concurrency model litmus tests☆71Updated last year
- ☆27Updated last week
- CHERI-RISC-V model written in Sail☆55Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 3 months ago
- Sail RISC-V model☆461Updated last week
- Simple demonstration of using the RISC-V Vector extension☆37Updated 7 months ago
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆53Updated last week
- ☆35Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆131Updated 3 weeks ago
- Risc-V hypervisor for TEE development☆98Updated last year