Alternatives and similar repositories for riscv-j-extension

Users that are interested in riscv-j-extension are comparing it to the libraries listed below

• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated 2 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆151Updated 4 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆211Updated last year
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆184Updated this week
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• riscv-software-src / riscv-unified-db
  Machine-readable database of the RISC-V specification, and tools to generate various views
  ☆75Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆119Updated last week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆153Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 7 months ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆87Updated this week
• sifiveinc / wake
  The SiFive wake build tool
  ☆90Updated this week
• riscv / riscv-aia
  ☆89Updated 3 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆117Updated 2 weeks ago
• riscv-software-src / riscof
  ☆83Updated 2 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆169Updated 5 months ago
• chipsalliance / t1
  The highest performace Cray-like RISC-V Vector in the world.
  ☆272Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆179Updated last year
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆140Updated 2 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆148Updated last year
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆52Updated this week
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆42Updated last year
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆79Updated 3 weeks ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆100Updated 2 years ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆111Updated this week
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆117Updated last week
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated this week
• riscv-non-isa / riscv-semihosting
  ☆30Updated this week
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆72Updated this week