Working Draft of the RISC-V J Extension Specification
☆195Mar 6, 2026Updated 3 months ago
Alternatives and similar repositories for riscv-j-extension
Users that are interested in riscv-j-extension are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆91Aug 26, 2025Updated 9 months ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆297Jun 5, 2026Updated 2 weeks ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆95May 25, 2026Updated 3 weeks ago
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆40Mar 7, 2026Updated 3 months ago
- RISC-V Processor Trace Specification☆217Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- RISC-V Debug Specification Standard☆517Apr 8, 2026Updated 2 months ago
- CHERI-RISC-V model written in Sail☆66Jul 10, 2025Updated 11 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆226Jan 11, 2026Updated 5 months ago
- RISC-V Architecture Profiles☆189Apr 22, 2026Updated last month
- RISC-V Packed SIMD Extension☆173Jun 11, 2026Updated last week
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated 2 years ago
- RISC-V cryptography extensions standardisation work.☆414Mar 7, 2026Updated 3 months ago
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆70May 25, 2026Updated 3 weeks ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆152Jun 4, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆40Dec 8, 2024Updated last year
- ☆23Nov 12, 2020Updated 5 years ago
- ☆148Feb 29, 2024Updated 2 years ago
- ☆39Mar 6, 2026Updated 3 months ago
- The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…☆59Apr 8, 2026Updated 2 months ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- Sail RISC-V model☆720Updated this week
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 2 months ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆35May 20, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆32Apr 8, 2026Updated 2 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆74Jul 19, 2024Updated last year
- Easy SMT solver interaction☆36Feb 3, 2026Updated 4 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Main Repo for the OpenHW Group Software Task Group☆17Mar 11, 2025Updated last year
- RISC-V Security HC admin repo☆17Jan 7, 2025Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- ☆101Jun 11, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Port of Google v8 engine to RISC-V.☆246Nov 10, 2025Updated 7 months ago
- Refinement type checking and inference tool for Rust☆22Updated this week
- RISC-V IOMMU Specification☆164Jun 8, 2026Updated last week
- ☆16Nov 28, 2024Updated last year
- ☆376Updated this week
- Documentation for the RISC-V Supervisor Binary Interface☆474May 13, 2026Updated last month
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Apr 28, 2026Updated last month