openhwgroup / force-riscv
Instruction Set Generator initially contributed by Futurewei
☆272Updated last year
Alternatives and similar repositories for force-riscv:
Users that are interested in force-riscv are comparing it to the libraries listed below
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆455Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆221Updated 3 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆493Updated this week
- VeeR EL2 Core☆263Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆243Updated 3 months ago
- Common SystemVerilog components☆572Updated 2 weeks ago
- RISC-V CPU Core☆311Updated 8 months ago
- ☆225Updated 2 years ago
- Verilog Configurable Cache☆170Updated 2 months ago
- RISC-V Torture Test☆179Updated 7 months ago
- ☆168Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆244Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆205Updated 4 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆398Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆306Updated 2 months ago
- ☆303Updated 5 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆399Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- ☆275Updated last week
- Simple RISC-V 3-stage Pipeline in Chisel☆559Updated 6 months ago
- SystemC/TLM-2.0 Co-simulation framework☆232Updated 3 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆551Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆205Updated last week
- ☆538Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆183Updated 3 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 6 months ago
- A Linux-capable RISC-V multicore for and by the world☆658Updated last week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆356Updated this week