Alternatives and similar repositories for chisel-nix:

Users that are interested in chisel-nix are comparing it to the libraries listed below

• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆13Updated 3 weeks ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• chipsalliance / espresso
  ☆37Updated last year
• sequencer / zaozi
  The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project
  ☆25Updated this week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆46Updated 4 months ago
• OSCPU / openperf
  ☆11Updated 2 weeks ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆57Updated 3 years ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 4 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆28Updated 10 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆17Updated 7 months ago
• Anillc / Yuri
  A riscv emulator.
  ☆18Updated last year
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated 2 weeks ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated last week
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆112Updated 4 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆35Updated this week
• yamak / axi-nodes
  ☆19Updated 2 years ago
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆10Updated last month
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 10 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 7 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 9 months ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆24Updated last month
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆17Updated 2 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆16Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated last year
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆14Updated 5 months ago
• sequencer / arithmetic
  ☆32Updated 2 weeks ago