Nix template for the chisel-based industrial designing flows.
☆56Apr 23, 2025Updated 11 months ago
Alternatives and similar repositories for chisel-nix
Users that are interested in chisel-nix are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated last year
- The Scala parser to parse riscv/riscv-opcodes generate☆25Jan 21, 2026Updated 2 months ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆67Updated this week
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- ☆67Mar 3, 2026Updated 2 weeks ago
- ☆312Mar 14, 2026Updated last week
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- ☆36Jul 22, 2025Updated 8 months ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- The 'missing header' for Chisel☆24Feb 5, 2026Updated last month
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆23Sep 14, 2024Updated last year
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- ☆11Dec 23, 2025Updated 3 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆25Mar 8, 2026Updated 2 weeks ago
- ☆44Dec 5, 2025Updated 3 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated last year
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated last year
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- high-performance RTL simulator☆188Jun 19, 2024Updated last year
- Diff nix build logs with less clutter☆14Nov 7, 2024Updated last year
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- Microarchitecture diagrams of several CPUs☆47Mar 14, 2026Updated last week
- ☆16Updated this week
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆630Aug 13, 2024Updated last year
- Interpreter and compiler for the ISA specification language "Architecture Specification Language" (ASL)☆28Sep 8, 2025Updated 6 months ago
- iEDA water-drop training initiative☆14Sep 10, 2024Updated last year
- An open-source EDA infrastructure and tools from netlist to GDS☆491Mar 11, 2026Updated last week
- ☆30Jan 23, 2025Updated last year
- ☆22Nov 25, 2023Updated 2 years ago
- Xiangshan deterministic workloads generator☆24May 14, 2025Updated 10 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 10 months ago
- A framework for ysyx flow☆13Oct 31, 2024Updated last year
- Subscribe to updates from people you follow, from any platform to any platform☆14Mar 14, 2026Updated last week
- verilog module add prefix script 可用于ysyx项目添加学号☆13Mar 4, 2024Updated 2 years ago
- ☆81Oct 29, 2024Updated last year
- ☆71Feb 2, 2026Updated last month
- 关于移植模型至gemmini的文档☆33May 4, 2022Updated 3 years ago