The Ultra-Low Power RISC-V Core
☆1,867Aug 6, 2025Updated 11 months ago
Alternatives and similar repositories for e203_hbirdv2
Users that are interested in e203_hbirdv2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,849Mar 24, 2021Updated 5 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆178Dec 5, 2023Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,270Sep 18, 2021Updated 4 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,248Jun 27, 2024Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,743Sep 18, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open-source high-performance RISC-V processor☆7,122Updated this week
- IC design and development should be faster,simpler and more reliable☆2,002Dec 31, 2021Updated 4 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,579May 12, 2026Updated last month
- A very simple and easy to understand RISC-V core.☆1,489Nov 9, 2023Updated 2 years ago
- Must-have verilog systemverilog modules☆1,989Mar 12, 2026Updated 3 months ago
- Rocket Chip Generator☆3,803Jun 2, 2026Updated last month
- OpenXuantie - OpenC910 Core☆1,448Jun 28, 2024Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,997Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,185Feb 11, 2026Updated 4 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- VeeR EH1 core☆952May 29, 2023Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,616Updated this week
- Verilog AXI components for FPGA implementation☆2,082Feb 27, 2025Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,944Updated this week
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 3 years ago
- A small, light weight, RISC CPU soft core☆1,559Dec 8, 2025Updated 7 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆922Jun 27, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,258May 29, 2026Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,194Jun 26, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,309Jun 26, 2026Updated last week
- AMBA bus lecture material☆538Jan 21, 2020Updated 6 years ago
- RISC-V SoC designed by students in UCAS☆1,534Jun 5, 2026Updated last month
- RTL, Cmodel, and testbench for NVDLA☆2,114Mar 2, 2022Updated 4 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆615Aug 9, 2024Updated last year
- Chisel: A Modern Hardware Design Language☆4,711Updated this week
- GNU toolchain for RISC-V, including GCC☆4,553Jun 6, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,826Jun 17, 2026Updated 3 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆988Nov 15, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V Cores, SoC platforms and SoCs☆928Mar 26, 2021Updated 5 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,707Jun 30, 2026Updated last week
- RISC-V CPU Core☆441Jun 24, 2025Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆606Oct 10, 2021Updated 4 years ago
- 帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目☆5,537May 15, 2022Updated 4 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆314Updated this week
- ☆2,134Updated this week