The Ultra-Low Power RISC-V Core
☆1,925Sep 25, 2026Updated this week
Alternatives and similar repositories for e203_hbirdv2
Users that are interested in e203_hbirdv2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,854Mar 24, 2021Updated 5 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆179Dec 5, 2023Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,312Sep 18, 2021Updated 5 years ago
- Open-source high-performance RISC-V processor☆7,275Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,384Sep 7, 2026Updated 2 weeks ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- RISC-V CPU Core (RV32IM)☆1,796Sep 18, 2021Updated 5 years ago
- OpenXuantie - OpenC910 Core☆1,478Jun 28, 2024Updated 2 years ago
- IC design and development should be faster，simpler and more reliable☆2,022Dec 31, 2021Updated 4 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,612Sep 4, 2026Updated 3 weeks ago
- A very simple and easy to understand RISC-V core.☆1,535Nov 9, 2023Updated 2 years ago
- Must-have verilog systemverilog modules☆2,021Mar 12, 2026Updated 6 months ago
- Rocket Chip Generator☆3,873Sep 13, 2026Updated 2 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,129Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,273Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- VeeR EH1 core☆970Jul 16, 2026Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,706Updated this week
- Verilog AXI components for FPGA implementation☆2,145Feb 27, 2025Updated last year
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,068Updated this week
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 4 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,245Sep 11, 2026Updated 2 weeks ago
- A small, light weight, RISC CPU soft core☆1,586Sep 16, 2026Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,399Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆955Aug 18, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,299Aug 26, 2026Updated last month
- AMBA bus lecture material☆554Jan 21, 2020Updated 6 years ago
- RISC-V SoC designed by students in UCAS☆1,554Updated this week
- RTL, Cmodel, and testbench for NVDLA☆2,170Mar 2, 2022Updated 4 years ago
- Chisel: A Modern Hardware Design Language☆4,791Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆619Aug 9, 2024Updated 2 years ago
- ☆2,273Updated this week
- GNU toolchain for RISC-V, including GCC☆4,624Aug 27, 2026Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,888Aug 25, 2026Updated last month
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,004Nov 15, 2024Updated last year
- RISC-V Cores, SoC platforms and SoCs☆928Mar 26, 2021Updated 5 years ago
- RISC-V CPU Core☆451Jun 24, 2025Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆636Oct 10, 2021Updated 4 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,957Updated this week
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆5,758May 15, 2022Updated 4 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆328Sep 15, 2026Updated last week