riscv-mcu / e203_hbirdv2Links
The Ultra-Low Power RISC-V Core
☆1,656Updated 3 months ago
Alternatives and similar repositories for e203_hbirdv2
Users that are interested in e203_hbirdv2 are comparing it to the libraries listed below
Sorting:
- RISC-V CPU Core (RV32IM)☆1,589Updated 4 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,014Updated 2 weeks ago
- Must-have verilog systemverilog modules☆1,877Updated 3 months ago
- OpenXuantie - OpenC910 Core☆1,347Updated last year
- 32-bit Superscalar RISC-V CPU☆1,132Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,414Updated last week
- Verilog AXI components for FPGA implementation☆1,864Updated 9 months ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,784Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,144Updated 6 months ago
- RISC-V Cores, SoC platforms and SoCs☆904Updated 4 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,086Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,044Updated last week
- Verilog PCI express components☆1,460Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,686Updated last week
- Random instruction generator for RISC-V processor verification☆1,206Updated last month
- Various HDL (Verilog) IP Cores☆844Updated 4 years ago
- VeeR EH1 core☆912Updated 2 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,920Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,019Updated 6 months ago
- HDLBits website practices & solutions☆762Updated last year
- Digital Design with Chisel☆878Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆942Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆599Updated 7 years ago
- ☆1,086Updated this week
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆366Updated 2 years ago
- Documentation for XiangShan☆426Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,800Updated last year
- chisel tutorial exercises and answers☆736Updated 3 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,170Updated 2 years ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆419Updated 2 years ago