riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
☆1,361Updated 3 months ago
Alternatives and similar repositories for e203_hbirdv2:
Users that are interested in e203_hbirdv2 are comparing it to the libraries listed below
- RISC-V CPU Core (RV32IM)☆1,325Updated 3 years ago
- OpenXuantie - OpenC910 Core☆1,194Updated 6 months ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,649Updated 3 years ago
- Must-have verilog systemverilog modules☆1,691Updated 2 months ago
- Verilog AXI components for FPGA implementation☆1,580Updated last year
- 32-bit Superscalar RISC-V CPU☆915Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,180Updated last week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆887Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,000Updated 4 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆999Updated 5 months ago
- Random instruction generator for RISC-V processor verification☆1,051Updated 4 months ago
- VeeR EH1 core☆836Updated last year
- RISC-V Cores, SoC platforms and SoCs☆855Updated 3 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,441Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,721Updated this week
- RISC-V Tools (ISA Simulator and Tests)☆1,152Updated 2 years ago
- Verilog PCI express components☆1,183Updated 8 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,545Updated 2 months ago
- Documentation for XiangShan☆394Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,784Updated 3 months ago
- chisel tutorial exercises and answers☆706Updated 3 years ago
- Digital Design with Chisel☆795Updated last week
- Various HDL (Verilog) IP Cores☆724Updated 3 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,216Updated 6 months ago
- Scala based HDL☆1,706Updated this week
- educational microarchitectures for risc-v isa☆697Updated 5 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆887Updated 2 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆555Updated 5 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆668Updated last week
- The RIFFA development repository☆792Updated 7 months ago