riscv-mcu / e203_hbirdv2Links
The Ultra-Low Power RISC-V Core
☆1,598Updated last month
Alternatives and similar repositories for e203_hbirdv2
Users that are interested in e203_hbirdv2 are comparing it to the libraries listed below
Sorting:
- RISC-V CPU Core (RV32IM)☆1,537Updated 4 years ago
- OpenXuantie - OpenC910 Core☆1,314Updated last year
- Must-have verilog systemverilog modules☆1,839Updated last month
- 32-bit Superscalar RISC-V CPU☆1,094Updated 4 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,762Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,369Updated last week
- Verilog AXI components for FPGA implementation☆1,813Updated 6 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆991Updated last month
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,069Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,117Updated 3 months ago
- RISC-V Cores, SoC platforms and SoCs☆894Updated 4 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,628Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,966Updated this week
- Random instruction generator for RISC-V processor verification☆1,166Updated 3 months ago
- Verilog PCI express components☆1,423Updated last year
- Various HDL (Verilog) IP Cores☆832Updated 4 years ago
- Digital Design with Chisel☆859Updated this week
- VeeR EH1 core☆894Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,969Updated 4 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆934Updated 10 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,667Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,872Updated 2 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆588Updated last year
- Scala based HDL☆1,848Updated last week
- chisel tutorial exercises and answers☆736Updated 3 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆593Updated 7 years ago
- educational microarchitectures for risc-v isa☆718Updated 2 weeks ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆417Updated 2 years ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆362Updated 2 years ago