The Ultra-Low Power RISC-V Core
☆1,977Sep 25, 2026Updated last month
Alternatives and similar repositories for e203_hbirdv2
Users that are interested in e203_hbirdv2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,855Mar 24, 2021Updated 5 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆181Dec 5, 2023Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,329Sep 18, 2021Updated 5 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated last month
- RISC-V CPU Core (RV32IM)☆1,815Sep 18, 2021Updated 5 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,634Oct 12, 2026Updated 3 weeks ago
- Open-source high-performance RISC-V processor☆7,368Updated this week
- IC design and development should be faster,simpler and more reliable☆2,033Dec 31, 2021Updated 4 years ago
- A very simple and easy to understand RISC-V core.☆1,562Nov 9, 2023Updated 2 years ago
- OpenXuantie - OpenC910 Core☆1,490Jun 28, 2024Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,184Updated this week
- Rocket Chip Generator☆3,897Sep 13, 2026Updated last month
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,302Oct 13, 2026Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,747Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Must-have verilog systemverilog modules☆2,030Mar 12, 2026Updated 7 months ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,159Updated this week
- Verilog AXI components for FPGA implementation☆2,170Feb 27, 2025Updated last year
- VeeR EH1 core☆972Jul 16, 2026Updated 3 months ago
- AMBA bus lecture material☆562Jan 21, 2020Updated 6 years ago
- A small, light weight, RISC CPU soft core☆1,596Sep 16, 2026Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,280Updated this week
- RISC-V CPU Core☆454Jun 24, 2025Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,446Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆971Oct 26, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,320Updated this week
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 4 years ago
- RISC-V SoC designed by students in UCAS☆1,563Oct 27, 2026Updated last week
- ☆2,383Updated this week
- RTL, Cmodel, and testbench for NVDLA☆2,195Mar 2, 2022Updated 4 years ago
- SERV - The SErial RISC-V CPU☆1,916Aug 25, 2026Updated 2 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆646Oct 10, 2021Updated 5 years ago
- Various HDL (Verilog) IP Cores☆940Jul 1, 2021Updated 5 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Chisel: A Modern Hardware Design Language☆4,829Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆333Sep 15, 2026Updated last month
- Common SystemVerilog components☆814Sep 18, 2026Updated last month
- Simple RISC-V 3-stage Pipeline in Chisel☆621Aug 9, 2024Updated 2 years ago
- RV64GC Linux Capable RISC-V Core☆74Aug 7, 2026Updated 2 months ago
- GNU toolchain for RISC-V, including GCC☆4,658Oct 29, 2026Updated last week
- OpenTitan: Open source silicon root of trust☆3,741Updated this week