Alternatives and similar repositories for hbird-sdk:

Users that are interested in hbird-sdk are comparing it to the libraries listed below

• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆142Updated 8 months ago
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆112Updated 3 years ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆137Updated 8 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆126Updated 5 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆312Updated 10 months ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆132Updated 8 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆114Updated 5 years ago
• ljgibbslf / SM3_core
  ☆140Updated 4 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆246Updated 4 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆266Updated this week
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆192Updated last year
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆122Updated 4 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆114Updated 2 years ago
• Lichee-Pi / Tang_E203_Mini
  LicheeTang 蜂鸟E203 Core
  ☆190Updated 5 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆308Updated 3 months ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆109Updated 10 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆273Updated last year
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆403Updated last month
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆139Updated 2 weeks ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆78Updated 2 months ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆193Updated 7 months ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆146Updated 8 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆136Updated 3 weeks ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆140Updated 2 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆68Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• jamieiles / uart
  Verilog UART
  ☆146Updated 11 years ago