riscv-mcu / hbird-sdk
OpenSource HummingBird RISC-V Software Development Kit
☆142Updated 11 months ago
Related projects ⓘ
Alternatives and complementary repositories for hbird-sdk
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆110Updated 3 years ago
- OpenXuantie - OpenE902 Core☆136Updated 4 months ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆99Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆129Updated 4 months ago
- OpenXuantie - OpenE906 Core☆134Updated 4 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆199Updated 4 years ago
- ☆141Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆122Updated 5 years ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆171Updated last year
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆53Updated last year
- ☆137Updated this week
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆66Updated 3 years ago
- Vivado诸多IP,包括图像处理等☆161Updated 3 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆258Updated 4 years ago
- ☆73Updated 9 months ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆114Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆258Updated 6 months ago
- LicheeTang 蜂鸟E203 Core☆185Updated 5 years ago
- ☆63Updated 2 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆75Updated 4 years ago
- AXI协议规范中文翻译版☆130Updated 2 years ago
- ☆36Updated 2 years ago
- Cortex M0 based SoC☆70Updated 3 years ago
- VeeR EL2 Core☆252Updated this week
- SystemC/TLM-2.0 Co-simulation framework☆222Updated 2 weeks ago
- OpenXuantie - OpenC906 Core☆322Updated 4 months ago
- An AXI4 crossbar implementation in SystemVerilog☆121Updated 5 months ago
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago