AMBA bus lecture material
☆526Jan 21, 2020Updated 6 years ago
Alternatives and similar repositories for AMBA_AXI_AHB_APB
Users that are interested in AMBA_AXI_AHB_APB are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆140May 14, 2021Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆242Jul 16, 2023Updated 2 years ago
- Verilog AXI components for FPGA implementation☆2,010Feb 27, 2025Updated last year
- AMBA bus generator including AXI, AHB, and APB☆122Jul 29, 2021Updated 4 years ago
- AMBA AXI VIP☆456Jun 28, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆160Mar 31, 2020Updated 6 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆196Jul 23, 2018Updated 7 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,546Updated this week
- Verification IP for APB protocol☆75Dec 18, 2020Updated 5 years ago
- AXI Interconnect☆56Aug 20, 2021Updated 4 years ago
- AXI DMA 32 / 64 bits☆125Jul 17, 2014Updated 11 years ago
- Verilog PCI express components☆1,568Apr 26, 2024Updated last year
- ☆38Aug 12, 2015Updated 10 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆33Aug 1, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆78Oct 7, 2022Updated 3 years ago
- Various HDL (Verilog) IP Cores☆889Jul 1, 2021Updated 4 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆585Oct 10, 2021Updated 4 years ago
- AHB DMA 32 / 64 bits☆62Jul 17, 2014Updated 11 years ago
- ☆29May 11, 2021Updated 4 years ago
- The Ultra-Low Power RISC-V Core☆1,806Aug 6, 2025Updated 8 months ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- ☆13Jun 4, 2020Updated 5 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- IC design and development should be faster,simpler and more reliable☆1,986Dec 31, 2021Updated 4 years ago
- ☆77Jan 19, 2016Updated 10 years ago
- Must-have verilog systemverilog modules☆1,948Mar 12, 2026Updated last month
- ☆18Apr 5, 2015Updated 11 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆58Apr 9, 2021Updated 5 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆105Aug 9, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- VIP for AXI Protocol☆169May 24, 2022Updated 3 years ago
- UVM AHB VIP☆97Sep 13, 2025Updated 7 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47May 10, 2024Updated last year
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆135Nov 29, 2017Updated 8 years ago
- Verification IP for I2C protocol☆52Sep 22, 2021Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆40Jun 27, 2021Updated 4 years ago