Alternatives and similar repositories for AMBA_AXI_AHB_APB

Users that are interested in AMBA_AXI_AHB_APB are comparing it to the libraries listed below

• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆413Updated last year
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆316Updated 3 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆36Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆211Updated 2 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆175Updated 7 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆251Updated 12 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆277Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆128Updated 4 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆560Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆359Updated last year
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆222Updated 7 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆201Updated 4 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆50Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆116Updated 11 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆431Updated 3 years ago
• gillianGan / ahb_sram_master
  ☆19Updated 5 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆202Updated last year
• hxfycy / 1024-point-fft
  Radix-4 1024 point fft in verilog
  ☆10Updated 5 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆267Updated last year
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆122Updated 7 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆93Updated 3 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆142Updated 3 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆152Updated 5 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆817Updated 5 months ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆33Updated 5 months ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆141Updated last month
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆105Updated 7 months ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆104Updated 7 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆140Updated 4 years ago