adki / AMBA_AXI_AHB_APBView external linksLinks
AMBA bus lecture material
☆508Jan 21, 2020Updated 6 years ago
Alternatives and similar repositories for AMBA_AXI_AHB_APB
Users that are interested in AMBA_AXI_AHB_APB are comparing it to the libraries listed below
Sorting:
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆238Jul 16, 2023Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Jul 29, 2021Updated 4 years ago
- Verilog AXI components for FPGA implementation☆1,952Feb 27, 2025Updated 11 months ago
- AMBA AXI VIP☆447Jun 28, 2024Updated last year
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆160Mar 31, 2020Updated 5 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆191Jul 23, 2018Updated 7 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,492Updated this week
- Verification IP for APB protocol☆75Dec 18, 2020Updated 5 years ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- Various HDL (Verilog) IP Cores☆873Jul 1, 2021Updated 4 years ago
- Verilog PCI express components☆1,533Apr 26, 2024Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆560Oct 10, 2021Updated 4 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- ☆38Aug 12, 2015Updated 10 years ago
- AXI DMA 32 / 64 bits☆124Jul 17, 2014Updated 11 years ago
- The Ultra-Low Power RISC-V Core☆1,733Aug 6, 2025Updated 6 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Mar 17, 2022Updated 3 years ago
- Must-have verilog systemverilog modules☆1,926Aug 2, 2025Updated 6 months ago
- ☆27May 11, 2021Updated 4 years ago
- UVM AHB VIP☆93Sep 13, 2025Updated 5 months ago
- VIP for AXI Protocol☆164May 24, 2022Updated 3 years ago
- AHB DMA 32 / 64 bits☆59Jul 17, 2014Updated 11 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆33Aug 1, 2020Updated 5 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆101Aug 9, 2024Updated last year
- ☆74Jan 19, 2016Updated 10 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47May 10, 2024Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆74Oct 7, 2022Updated 3 years ago
- IC design and development should be faster,simpler and more reliable☆1,988Dec 31, 2021Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 8 years ago
- Verification IP for I2C protocol☆51Sep 22, 2021Updated 4 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 5 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- Verilog AXI stream components for FPGA implementation☆859Feb 27, 2025Updated 11 months ago
- Verilog UART☆534Feb 27, 2025Updated 11 months ago
- An uvm verification env for ahb2apb bridge☆58Apr 9, 2021Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆35Mar 9, 2017Updated 8 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆136Nov 29, 2017Updated 8 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Aug 10, 2022Updated 3 years ago