Alternatives and similar repositories for AMBA_AXI_AHB_APB

Users that are interested in AMBA_AXI_AHB_APB are comparing it to the libraries listed below

• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆401Updated 11 months ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆205Updated last year
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆300Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆124Updated 4 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆349Updated last year
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆247Updated 11 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆172Updated 6 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆271Updated 3 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆541Updated 3 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆262Updated last year
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆86Updated 3 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆193Updated 4 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆200Updated last year
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆35Updated last year
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆217Updated 7 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆246Updated 7 months ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆189Updated 8 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆114Updated 10 years ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆136Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,287Updated last week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆808Updated 3 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆467Updated 3 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆150Updated 5 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆136Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆154Updated 2 weeks ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆150Updated 2 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆423Updated 2 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆209Updated 10 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆429Updated last month
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆119Updated 7 years ago