Alternatives and similar repositories for AMBA_AXI_AHB_APB

Users that are interested in AMBA_AXI_AHB_APB are comparing it to the libraries listed below

• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆433Updated last year
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆334Updated 3 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆39Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆228Updated 2 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆187Updated 7 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆263Updated 12 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆583Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆133Updated 4 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆283Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆397Updated 2 months ago
• gillianGan / ahb_sram_master
  ☆19Updated 5 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆210Updated 5 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆276Updated 2 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆230Updated 8 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆439Updated 3 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆131Updated 8 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆53Updated last year
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆165Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• hxfycy / 1024-point-fft
  Radix-4 1024 point fft in verilog
  ☆13Updated 5 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆105Updated 3 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆159Updated 3 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆113Updated 11 months ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆156Updated 5 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆209Updated 2 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆203Updated 8 years ago
• Advanced-Microelectronics-Group / OpenC910_Modified
  commit rtl and build cosim env
  ☆36Updated last year
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆843Updated 9 months ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆159Updated 3 years ago