A DDR3 memory controller in Verilog for various FPGAs
☆591Oct 10, 2021Updated 4 years ago
Alternatives and similar repositories for core_ddr3_controller
Users that are interested in core_ddr3_controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Opensource DDR3 Controller☆431Jan 18, 2026Updated 4 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆94Feb 28, 2018Updated 8 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆89Apr 8, 2024Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆81Dec 1, 2022Updated 3 years ago
- Various HDL (Verilog) IP Cores☆902Jul 1, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆79Feb 4, 2021Updated 5 years ago
- Verilog PCI express components☆1,596Apr 26, 2024Updated 2 years ago
- Verilog AXI components for FPGA implementation☆2,044Feb 27, 2025Updated last year
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 14 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆376Mar 15, 2026Updated 2 months ago
- Verilog SDRAM memory controller☆368May 13, 2017Updated 9 years ago
- Small footprint and configurable DRAM core☆502May 12, 2026Updated last week
- A simple DDR3 memory controller☆64Jan 9, 2023Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,247Sep 18, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- AMBA bus lecture material☆533Jan 21, 2020Updated 6 years ago
- Verilog I2C interface for FPGA implementation☆701Feb 27, 2025Updated last year
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆210Sep 15, 2023Updated 2 years ago
- Verilog Ethernet components for FPGA implementation☆2,959Feb 27, 2025Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆451Feb 13, 2026Updated 3 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,581Updated this week
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- Generic Register Interface (contains various adapters)☆140Feb 24, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Common SystemVerilog components☆747May 7, 2026Updated last week
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Verilog library for ASIC and FPGA designers☆1,415May 8, 2024Updated 2 years ago
- Minimal DVI / HDMI Framebuffer☆86Aug 9, 2020Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆100Jun 6, 2020Updated 5 years ago
- The Ultra-Low Power RISC-V Core☆1,833Aug 6, 2025Updated 9 months ago
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。☆338Sep 14, 2023Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,719Sep 18, 2021Updated 4 years ago
- Verilog UART☆562Feb 27, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A simple, basic, formally verified UART controller☆338Jan 29, 2024Updated 2 years ago
- USB -> AXI Debug Bridge☆44Jun 5, 2021Updated 4 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆189Mar 10, 2024Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆212Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆128Jul 22, 2021Updated 4 years ago
- Verilog AXI stream components for FPGA implementation☆890Feb 27, 2025Updated last year