ultraembedded / core_ddr3_controllerLinks
A DDR3 memory controller in Verilog for various FPGAs
☆542Updated 4 years ago
Alternatives and similar repositories for core_ddr3_controller
Users that are interested in core_ddr3_controller are comparing it to the libraries listed below
Sorting:
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆402Updated 3 months ago
- Bus bridges and other odds and ends☆612Updated 8 months ago
- Opensource DDR3 Controller☆402Updated 6 months ago
- Verilog UART☆515Updated 9 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆536Updated last month
- Various HDL (Verilog) IP Cores☆854Updated 4 years ago
- Verilog I2C interface for FPGA implementation☆664Updated 9 months ago
- Verilog SDRAM memory controller