Alternatives and similar repositories for core_ddr3_controller

Users that are interested in core_ddr3_controller are comparing it to the libraries listed below

• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆410Updated 3 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆523Updated 10 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆618Updated 9 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆406Updated this week
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆568Updated last week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆859Updated 4 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆673Updated 10 months ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆351Updated 8 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆694Updated 3 weeks ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆852Updated 10 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆282Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆305Updated 3 months ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆235Updated 2 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆497Updated 5 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆318Updated 2 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆319Updated last year
• jamieiles / uart
  Verilog UART
  ☆188Updated 12 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆438Updated last year
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆451Updated 7 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆708Updated 2 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆474Updated 2 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆693Updated last month
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆559Updated 2 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆219Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆557Updated 2 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆491Updated 2 weeks ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆340Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,453Updated last month
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆336Updated last year
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆346Updated 2 months ago