ultraembedded / core_ddr3_controllerLinks
A DDR3 memory controller in Verilog for various FPGAs
☆528Updated 4 years ago
Alternatives and similar repositories for core_ddr3_controller
Users that are interested in core_ddr3_controller are comparing it to the libraries listed below
Sorting:
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆386Updated last month
- Opensource DDR3 Controller☆390Updated 4 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆459Updated this week
- Verilog UART☆511Updated 8 months ago
- Verilog I2C interface for FPGA implementation☆655Updated 8 months ago
- Various HDL (Verilog) IP Cores☆842Updated 4 years ago
- Bus bridges and other odds and ends☆602Updated 6 months ago
- Verilog SDRAM memory controller☆348Updated 8 years ago
- Common SystemVerilog components☆672Updated 2 weeks ago
- AXI interface modules for Cocotb☆296Updated last month
- Verilog AXI stream components for FPGA implementation☆838Updated 8 months ago
- Verilog UART☆185Updated 12 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆328Updated 3 weeks ago
- SPI Master for FPGA - VHDL and Verilog☆305Updated 2 years ago
- AMBA bus lecture material☆474Updated 5 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- AMBA AXI VIP☆426Updated last year
- synthesiseable ieee 754 floating point library in verilog☆684Updated 2 years ago
- Basic RISC-V Test SoC☆158Updated 6 years ago
- The UVM written in Python☆479Updated this week
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆224Updated 2 years ago
- SystemVerilog to Verilog conversion☆671Updated last week
- SPI Slave for FPGA in Verilog and VHDL☆214Updated last year
- training labs and examples☆435Updated 3 years ago
- High throughput JPEG decoder in Verilog for FPGA☆243Updated 3 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆268Updated 2 years ago
- Awesome ASIC design verification☆329Updated 3 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆446Updated 5 months ago
- lowRISC Style Guides☆462Updated 4 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago