ultraembedded / core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
☆423Updated 3 years ago
Alternatives and similar repositories for core_ddr3_controller:
Users that are interested in core_ddr3_controller are comparing it to the libraries listed below
- Opensource DDR3 Controller☆279Updated this week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆313Updated 10 months ago
- Bus bridges and other odds and ends☆523Updated last month
- Common SystemVerilog components☆587Updated 2 weeks ago
- Various HDL (Verilog) IP Cores☆751Updated 3 years ago
- AXI interface modules for Cocotb☆244Updated last year
- Verilog UART☆459Updated 2 weeks ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- Verilog SDRAM memory controller☆321Updated 7 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,233Updated 2 weeks ago
- Verilog AXI stream components for FPGA implementation☆790Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆601Updated 3 weeks ago
- Verilog I2C interface for FPGA implementation☆589Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆460Updated last month
- The UVM written in Python☆414Updated 2 months ago
- AMBA AXI VIP☆387Updated 8 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆405Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆506Updated this week
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆192Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆252Updated 2 months ago
- AMBA bus lecture material☆410Updated 5 years ago
- synthesiseable ieee 754 floating point library in verilog☆576Updated 2 years ago
- A simple, basic, formally verified UART controller☆292Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆228Updated 2 years ago
- lowRISC Style Guides☆400Updated 6 months ago
- Awesome ASIC design verification☆287Updated 3 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- Verilog PCI express components☆1,243Updated 10 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆559Updated last week