A DDR3 memory controller in Verilog for various FPGAs
☆644Oct 10, 2021Updated 5 years ago
Alternatives and similar repositories for core_ddr3_controller
Users that are interested in core_ddr3_controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Opensource DDR3 Controller☆497Sep 12, 2026Updated last month
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆98Feb 28, 2018Updated 8 years ago
- Various HDL (Verilog) IP Cores☆939Jul 1, 2021Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆85Dec 1, 2022Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆94Apr 8, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Verilog PCI express components☆1,676Apr 26, 2024Updated 2 years ago
- ☆84Feb 4, 2021Updated 5 years ago
- DDR2 memory controller written in Verilog☆86Feb 28, 2012Updated 14 years ago
- Small footprint and configurable DRAM core☆568Updated this week
- Verilog AXI components for FPGA implementation☆2,167Feb 27, 2025Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆497Oct 17, 2026Updated 2 weeks ago
- AMBA bus lecture material☆562Jan 21, 2020Updated 6 years ago
- 32-bit Superscalar RISC-V CPU☆1,327Sep 18, 2021Updated 5 years ago
- Verilog SDRAM memory controller☆388May 13, 2017Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆223Sep 15, 2023Updated 3 years ago
- A simple DDR3 memory controller☆68Aug 20, 2026Updated 2 months ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆423Aug 10, 2026Updated 2 months ago
- Verilog library for ASIC and FPGA designers☆1,440May 8, 2024Updated 2 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,742Updated this week
- Verilog Ethernet components for FPGA implementation☆3,143Feb 27, 2025Updated last year
- Verilog I2C interface for FPGA implementation☆731Feb 27, 2025Updated last year
- Basic RISC-V Test SoC☆212Apr 7, 2019Updated 7 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆252Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 6 years ago
- Common SystemVerilog components☆812Sep 18, 2026Updated last month
- Verilog UART☆591Feb 27, 2025Updated last year
- The Ultra-Low Power RISC-V Core☆1,966Sep 25, 2026Updated last month
- RISC-V CPU Core (RV32IM)☆1,811Sep 18, 2021Updated 5 years ago
- synthesiseable ieee 754 floating point library in verilog☆763Mar 13, 2023Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆140Jul 11, 2025Updated last year
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated 2 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆194Mar 10, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- The multi-core cluster of a PULP system.☆123Updated this week
- Verilog digital signal processing components☆197Oct 30, 2022Updated 4 years ago
- A simple, basic, formally verified UART controller☆356Jan 29, 2024Updated 2 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- Bus bridges and other odds and ends☆714Sep 11, 2026Updated last month
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。☆351Sep 14, 2023Updated 3 years ago