Alternatives and similar repositories for core_ddr3_controller

Users that are interested in core_ddr3_controller are comparing it to the libraries listed below

• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆392Updated 2 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆393Updated 5 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆514Updated 9 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆657Updated 9 months ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆480Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆609Updated 7 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆675Updated last week
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆351Updated 8 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆847Updated 4 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆298Updated 2 months ago
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆841Updated 9 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆677Updated last week
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆430Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆544Updated last month
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆447Updated 6 months ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆482Updated 5 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,414Updated last week
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆333Updated 3 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆483Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆468Updated 3 weeks ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆696Updated 2 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆225Updated 2 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆439Updated 3 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆309Updated 2 years ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆540Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆161Updated 6 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆316Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆622Updated last week