pConst / basic_verilog
Must-have verilog systemverilog modules
☆1,750Updated 4 months ago
Alternatives and similar repositories for basic_verilog:
Users that are interested in basic_verilog are comparing it to the libraries listed below
- Verilog AXI components for FPGA implementation☆1,665Updated last month
- Various HDL (Verilog) IP Cores☆769Updated 3 years ago
- Verilog PCI express components☆1,254Updated 11 months ago
- HDLBits website practices & solutions☆727Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,246Updated last week
- The Ultra-Low Power RISC-V Core☆1,451Updated 5 months ago
- Verilog AXI stream components for FPGA implementation☆793Updated last month
- 数字IC相关资料☆1,098Updated 4 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆567Updated 7 years ago
- The RIFFA development repository☆809Updated 9 months ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆347Updated last year
- Verilog Ethernet components for FPGA implementation☆2,492Updated last month
- HDL libraries and projects☆1,614Updated this week
- Verilog I2C interface for FPGA implementation☆596Updated last month
- Verilog UART☆467Updated last month
- Verilog library for ASIC and FPGA designers☆1,266Updated 10 months ago
- 在vscode上的数字设计开发插件☆361Updated 2 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆561Updated last year
- AMBA bus lecture material☆417Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆975Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆594Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,405Updated 3 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆427Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,033Updated last month
- Common SystemVerilog components☆595Updated 2 weeks ago
- ☆609Updated 9 months ago
- A small, light weight, RISC CPU soft core☆1,371Updated last month
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆318Updated 11 months ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆652Updated 4 months ago
- ☆663Updated 4 months ago