pConst / basic_verilog
Must-have verilog systemverilog modules
☆1,768Updated last month
Alternatives and similar repositories for basic_verilog
Users that are interested in basic_verilog are comparing it to the libraries listed below
Sorting:
- Verilog AXI components for FPGA implementation☆1,713Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,272Updated last week
- Verilog PCI express components☆1,289Updated last year
- The Ultra-Low Power RISC-V Core☆1,490Updated 7 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆573Updated 7 years ago
- Various HDL (Verilog) IP Cores☆786Updated 3 years ago
- Verilog AXI stream components for FPGA implementation☆802Updated 2 months ago
- HDL libraries and projects☆1,643Updated this week
- Verilog library for ASIC and FPGA designers☆1,282Updated last year
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆348Updated last year
- HDLBits website practices & solutions☆734Updated last year
- Verilog Ethernet components for FPGA implementation☆2,546Updated 2 months ago
- The RIFFA development repository☆828Updated 11 months ago
- Verilog UART☆480Updated 2 months ago
- 数字IC相关资料☆1,138Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,014Updated 3 years ago
- Verilog I2C interface for FPGA implementation☆606Updated 2 months ago
- AMBA bus lecture material☆434Updated 5 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,535Updated last week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆530Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,065Updated 3 months ago
- Random instruction generator for RISC-V processor verification☆1,113Updated 3 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆454Updated 3 years ago
- 在vscode上的数字设计开发插件☆373Updated 2 years ago
- cocotb: Python-based chip (RTL) verification☆1,967Updated last week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆950Updated 3 weeks ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,035Updated 8 months ago
- RISC-V CPU Core (RV32IM)☆1,441Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆633Updated 2 years ago
- Common SystemVerilog components☆618Updated last week