Alternatives and similar repositories for verilog-axi

Users that are interested in verilog-axi are comparing it to the libraries listed below

• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,406Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,353Updated last week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆819Updated 5 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,822Updated 2 weeks ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆828Updated 4 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆640Updated 5 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆593Updated 7 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆502Updated 5 months ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆839Updated last year
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,568Updated 2 weeks ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆456Updated 5 years ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,058Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,330Updated last year
• alexforencich / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆2,664Updated 5 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,109Updated 2 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆649Updated this week
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆564Updated 3 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,086Updated 3 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆984Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,153Updated 2 months ago
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,721Updated this week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,519Updated 3 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆664Updated 2 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆502Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,609Updated 2 weeks ago
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆671Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆363Updated last year
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆416Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆889Updated 2 years ago
• Digilent / vivado-library
  ☆631Updated 3 weeks ago