Alternatives and similar repositories for verilog-axi

Users that are interested in verilog-axi are comparing it to the libraries listed below

• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,343Updated this week
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,396Updated last year
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆817Updated 5 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,816Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆823Updated 4 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆840Updated last year
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆590Updated 7 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆637Updated 5 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆499Updated 5 months ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆454Updated 5 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,101Updated 2 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆642Updated last week
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆979Updated 2 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,069Updated 3 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,552Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,146Updated 2 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆663Updated 2 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,322Updated last year
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,708Updated this week
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆560Updated 3 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• alexforencich / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆2,654Updated 5 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,052Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆498Updated 3 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,056Updated 10 months ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆431Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆359Updated last year
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,600Updated last week
• Digilent / vivado-library
  ☆627Updated last week
• sudhamshu091 / 32-Verilog-Mini-Projects
  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …
  ☆4Updated 8 months ago