alexforencich / verilog-axiLinks
Verilog AXI components for FPGA implementation
☆1,919Updated 10 months ago
Alternatives and similar repositories for verilog-axi
Users that are interested in verilog-axi are comparing it to the libraries listed below
Sorting:
- Verilog PCI express components☆1,500Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,453Updated last month
- Verilog AXI stream components for FPGA implementation☆852Updated 10 months ago
- Must-have verilog systemverilog modules☆1,901Updated 5 months ago
- Various HDL (Verilog) IP Cores☆859Updated 4 years ago
- The RIFFA development repository☆859Updated last year
- Verilog UART☆523Updated 10 months ago
- Verilog I2C interface for FPGA implementation☆669Updated 10 months ago
- AMBA bus lecture material☆495Updated 5 years ago
- The Ultra-Low Power RISC-V Core☆1,693Updated 5 months ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆591Updated 4 years ago
- Verilog Ethernet components for FPGA implementation☆2,820Updated 10 months ago
- Verilog library for ASIC and FPGA designers☆1,382Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆606Updated 7 years ago
- Random instruction generator for RISC-V processor verification☆1,236Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,169Updated 4 years ago
- Common SystemVerilog components☆692Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,158Updated 7 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆545Updated 4 years ago
- synthesiseable ieee 754 floating point library in verilog☆708Updated 2 years ago
- HDL libraries and projects☆1,824Updated this week
- Bus bridges and other odds and ends☆618Updated 8 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆556Updated last week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆407Updated 3 months ago
- cocotb: Python-based chip (RTL) verification☆2,210Updated this week
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆751Updated 2 years ago
- VeeR EH1 core☆918Updated 2 years ago
- training labs and examples☆443Updated 3 years ago
- ☆662Updated last week
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆370Updated 2 years ago