alexforencich / verilog-axiLinks
Verilog AXI components for FPGA implementation
☆1,762Updated 4 months ago
Alternatives and similar repositories for verilog-axi
Users that are interested in verilog-axi are comparing it to the libraries listed below
Sorting:
- Verilog PCI express components☆1,377Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,321Updated this week
- Verilog AXI stream components for FPGA implementation☆812Updated 4 months ago
- Must-have verilog systemverilog modules☆1,806Updated 3 months ago
- The RIFFA development repository☆838Updated last year
- Various HDL (Verilog) IP Cores☆818Updated 4 years ago
- Verilog UART☆494Updated 4 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆587Updated 7 years ago
- Verilog I2C interface for FPGA implementation☆625Updated 4 months ago
- Common SystemVerilog components☆634Updated last week
- cocotb: Python-based chip (RTL) verification☆2,025Updated this week
- AMBA bus lecture material☆448Updated 5 years ago
- synthesiseable ieee 754 floating point library in verilog☆657Updated 2 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆556Updated 3 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆971Updated 2 weeks ago
- Random instruction generator for RISC-V processor verification☆1,136Updated last month
- Verilog library for ASIC and FPGA designers☆1,309Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,090Updated last month
- Verilog Ethernet components for FPGA implementation☆2,625Updated 4 months ago
- The Ultra-Low Power RISC-V Core☆1,540Updated 9 months ago
- HDL libraries and projects☆1,689Updated this week
- A DDR3 memory controller in Verilog for various FPGAs☆492Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,053Updated 3 years ago
- Bus bridges and other odds and ends☆572Updated 3 months ago
- training labs and examples☆426Updated 2 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,050Updated 10 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆354Updated last year
- The UVM written in Python☆440Updated this week
- RISC-V CPU Core (RV32IM)☆1,496Updated 3 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆924Updated 8 months ago