Alternatives and similar repositories for XiangShan

Users that are interested in XiangShan are comparing it to the libraries listed below

• OSCPU / NutShell
  RISC-V SoC designed by students in UCAS
  ☆1,476Updated last month
• riscv / riscv-isa-manual
  RISC-V Instruction Set Manual
  ☆4,241Updated this week
• chipsalliance / chisel
  Chisel: A Modern Hardware Design Language
  ☆4,378Updated last week
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,538Updated this week
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,813Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,963Updated 4 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,948Updated this week
• SI-RISCV / e200_opensource
  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
  ☆2,753Updated 4 years ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,861Updated 2 months ago
• riscv-collab / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC
  ☆4,111Updated last week
• vortexgpgpu / vortex
  ☆1,645Updated this week
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,579Updated last month
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,306Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,605Updated last week
• gem5 / gem5
  The official repository for the gem5 computer-system architecture simulator.
  ☆2,179Updated this week
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆423Updated 2 weeks ago
• XUANTIE-RV / wujian100_open
  IC design and development should be faster，simpler and more reliable
  ☆1,969Updated 3 years ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,394Updated last month
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,045Updated last year
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,298Updated last year
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆791Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,172Updated 2 years ago
• mortbopet / Ripes
  A graphical processor simulator and assembly editor for the RISC-V ISA
  ☆3,023Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,646Updated last year
• llvm / circt
  Circuit IR Compilers and Tools
  ☆1,889Updated this week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,529Updated 3 years ago
• riscv-software-src / riscv-tests
  ☆1,051Updated 2 months ago
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,048Updated this week
• riscv-non-isa / riscv-asm-manual
  RISC-V Assembly Programmer's Manual
  ☆1,549Updated last week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,065Updated 11 months ago