OpenXiangShan / XiangShan

Related projects ⓘ

Alternatives and complementary repositories for XiangShan

• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,545Updated this week
• OSCPU / NutShell
  RISC-V SoC designed by students in UCAS
  ☆1,394Updated last week
• vortexgpgpu / vortex
  ☆1,234Updated this week
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,253Updated 2 weeks ago
• chipsalliance / chisel
  Chisel: A Modern Hardware Design Language
  ☆3,989Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,739Updated last month
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,163Updated 4 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,641Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,664Updated this week
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,435Updated this week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆2,995Updated last week
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,268Updated last month
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,115Updated last month
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆352Updated this week
• riscv-collab / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC
  ☆3,535Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,506Updated this week
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,488Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,139Updated 4 months ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆628Updated this week
• XUANTIE-RV / wujian100_open
  IC design and development should be faster，simpler and more reliable
  ☆1,868Updated 2 years ago
• SI-RISCV / e200_opensource
  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
  ☆2,632Updated 3 years ago
• riscv / riscv-isa-manual
  RISC-V Instruction Set Manual
  ☆3,684Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,279Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,437Updated this week
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,000Updated 2 months ago
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆968Updated 7 months ago
• steveicarus / iverilog
  Icarus Verilog
  ☆2,853Updated this week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆978Updated 2 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,258Updated 3 years ago
• llvm / circt
  Circuit IR Compilers and Tools
  ☆1,670Updated this week