Open-source high-performance RISC-V processor
☆7,310Oct 14, 2026Updated this week
Alternatives and similar repositories for XiangShan
Users that are interested in XiangShan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rocket Chip Generator☆3,885Sep 13, 2026Updated last month
- Chisel: A Modern Hardware Design Language☆4,809Updated this week
- Documentation for XiangShan☆445Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,261Updated this week
- OpenXuantie - OpenC910 Core☆1,479Jun 28, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,421Updated this week
- RISC-V SoC designed by students in UCAS☆1,560Sep 22, 2026Updated 3 weeks ago
- The Ultra-Low Power RISC-V Core☆1,939Sep 25, 2026Updated 2 weeks ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆957Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,160Updated this week
- ☆2,315Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆4,008Updated this week
- RISC-V Instruction Set Manual☆4,850Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,287Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,854Mar 24, 2021Updated 5 years ago
- Spike, a RISC-V ISA Simulator☆3,252Updated this week
- Digital Design with Chisel☆940Oct 5, 2026Updated last week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,165Sep 21, 2026Updated 3 weeks ago
- GNU toolchain for RISC-V, including GCC☆4,640Aug 27, 2026Updated last month
- IC design and development should be faster，simpler and more reliable☆2,026Dec 31, 2021Updated 4 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆352Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆620Aug 9, 2024Updated 2 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,391Sep 7, 2026Updated last month
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A template project for beginning new Chisel work☆708Feb 24, 2026Updated 7 months ago
- Berkeley's Spatial Array Generator☆1,510Updated this week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,106Updated this week
- VeeR EH1 core☆971Jul 16, 2026Updated 2 months ago
- The official repository for the gem5 computer-system architecture simulator.☆2,871Updated this week
- 32-bit Superscalar RISC-V CPU☆1,315Sep 18, 2021Updated 5 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,722Sep 24, 2026Updated 2 weeks ago
- Scala based HDL☆2,053Oct 6, 2026Updated last week
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆674Aug 13, 2024Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Random instruction generator for RISC-V processor verification☆1,366Sep 21, 2026Updated 3 weeks ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,626Updated this week
- OpenTitan: Open source silicon root of trust☆3,696Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,214Oct 3, 2026Updated last week
- Modern co-simulation framework for RISC-V CPUs☆188Updated this week
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 4 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆551Updated this week