Open-source high-performance RISC-V processor
☆6,996May 3, 2026Updated this week
Alternatives and similar repositories for XiangShan
Users that are interested in XiangShan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Documentation for XiangShan☆435Apr 29, 2026Updated last week
- Chisel: A Modern Hardware Design Language☆4,650Updated this week
- Rocket Chip Generator☆3,757Apr 21, 2026Updated 2 weeks ago
- RISC-V SoC designed by students in UCAS☆1,525Apr 28, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,148Mar 11, 2026Updated last month
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,234Updated this week
- OpenXuantie - OpenC910 Core☆1,430Jun 28, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,825Aug 6, 2025Updated 9 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆896Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,913Updated this week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,840Mar 24, 2021Updated 5 years ago
- Digital Design with Chisel☆914Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,587Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,133Feb 11, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V Instruction Set Manual☆4,598Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆607Aug 9, 2024Updated last year
- ☆1,996Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,130Sep 10, 2024Updated last year
- IC design and development should be faster,simpler and more reliable☆1,991Dec 31, 2021Updated 4 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆328Updated this week
- Spike, a RISC-V ISA Simulator☆3,083Updated this week
- GNU toolchain for RISC-V, including GCC☆4,466Updated this week
- A template project for beginning new Chisel work☆696Feb 24, 2026Updated 2 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- VeeR EH1 core☆938May 29, 2023Updated 2 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,127Jun 27, 2024Updated last year
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆636Aug 13, 2024Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,864Apr 14, 2026Updated 3 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆174Updated this week
- The official repository for the gem5 computer-system architecture simulator.☆2,592Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,566Apr 22, 2026Updated last week
- Scala based HDL☆1,977Apr 23, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Random instruction generator for RISC-V processor verification☆1,291Apr 3, 2026Updated last month
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,546Apr 27, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,170Feb 21, 2026Updated 2 months ago
- OpenTitan: Open source silicon root of trust☆3,340Updated this week
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 3 years ago
- Circuit IR Compilers and Tools☆2,107Updated this week
- Yosys Open SYnthesis Suite☆4,423Updated this week