Alternatives and similar repositories for NutShell

Users that are interested in NutShell are comparing it to the libraries listed below

• SI-RISCV / e200_opensource
  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
  ☆2,753Updated 4 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆423Updated 2 weeks ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,579Updated last month
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆561Updated 2 years ago
• trivialmips / nontrivial-mips
  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  ☆603Updated 5 years ago
• XUANTIE-RV / wujian100_open
  IC design and development should be faster，simpler and more reliable
  ☆1,969Updated 3 years ago
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,298Updated last year
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆791Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,172Updated 2 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,306Updated last year
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,963Updated 4 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,065Updated 11 months ago
• OSCPU / NutShell-doc
  ☆122Updated 3 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆989Updated 3 weeks ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,948Updated this week
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,538Updated this week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,529Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆588Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆857Updated this week
• cnrv / home
  为推广RISC-V尽些薄力
  ☆313Updated 2 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆896Updated 4 years ago
• riscv-software-src / riscv-tests
  ☆1,051Updated 2 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆662Updated 3 months ago
• xupsh / pp4fpgas-cn
  中文版 Parallel Programming for FPGAs
  ☆745Updated last year
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆589Updated last year
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆719Updated this week
• riscv-non-isa / riscv-elf-psabi-doc
  A RISC-V ELF psABI Document
  ☆802Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,861Updated 2 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,089Updated 3 years ago