OSCPU / NutShell

Related projects ⓘ

Alternatives and complementary repositories for NutShell

• SI-RISCV / e200_opensource
  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
  ☆2,630Updated 3 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,268Updated last month
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆543Updated last year
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,163Updated 4 months ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆352Updated this week
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,104Updated last year
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆628Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,739Updated last month
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,258Updated 3 years ago
• OSCPU / NutShell-doc
  ☆115Updated 2 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆978Updated 2 months ago
• XUANTIE-RV / wujian100_open
  IC design and development should be faster，simpler and more reliable
  ☆1,868Updated 2 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆845Updated this week
• cnrv / home
  为推广RISC-V尽些薄力
  ☆306Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,278Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,144Updated last year
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,641Updated this week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆836Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆545Updated 3 months ago
• riscv-software-src / riscv-tests
  ☆895Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆687Updated 3 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,371Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆864Updated 3 years ago
• trivialmips / nontrivial-mips
  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  ☆573Updated 4 years ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,253Updated last week
• vortexgpgpu / vortex
  ☆1,234Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆768Updated this week
• OpenXiangShan / XiangShan
  Open-source high-performance RISC-V processor
  ☆4,830Updated this week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆694Updated 2 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,017Updated 2 months ago