Alternatives and similar repositories for riscv

Users that are interested in riscv are comparing it to the libraries listed below

• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,066Updated 3 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,552Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,098Updated 2 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,595Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,144Updated last month
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆978Updated 2 weeks ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆894Updated 4 years ago
• riscv-software-src / riscv-tests
  ☆1,041Updated last month
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,915Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,834Updated 3 weeks ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,052Updated 10 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆925Updated 8 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆885Updated 2 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,296Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,339Updated last week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,603Updated last year
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,374Updated 2 weeks ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,944Updated 2 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆586Updated 11 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆718Updated 4 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆852Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,438Updated 5 months ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,568Updated this week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,779Updated 5 months ago
• riscv-non-isa / riscv-arch-test
  ☆580Updated this week
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆655Updated 2 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 2 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,615Updated last month
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆820Updated 4 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago