ultraembedded / riscvLinks
RISC-V CPU Core (RV32IM)
☆1,519Updated 3 years ago
Alternatives and similar repositories for riscv
Users that are interested in riscv are comparing it to the libraries listed below
Sorting:
- 32-bit Superscalar RISC-V CPU☆1,086Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,568Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,109Updated 2 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆984Updated last week
- Random instruction generator for RISC-V processor verification☆1,153Updated 2 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,937Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,609Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,353Updated last week
- ☆1,043Updated 2 months ago
- RISC-V Cores, SoC platforms and SoCs☆895Updated 4 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,058Updated 11 months ago
- VeeR EH1 core☆889Updated 2 years ago
- OpenXuantie - OpenC910 Core☆1,300Updated last year
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,391Updated last month
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,629Updated last year
- Verilog AXI components for FPGA implementation☆1,795Updated 5 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,846Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆926Updated 9 months ago
- A small, light weight, RISC CPU soft core☆1,449Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,956Updated 3 months ago
- educational microarchitectures for risc-v isa☆719Updated 5 months ago
- Verilog PCI express components☆1,406Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,588Updated last week
- Simple RISC-V 3-stage Pipeline in Chisel☆588Updated last year
- Digital Design with Chisel☆855Updated this week
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- Must-have verilog systemverilog modules☆1,822Updated 3 weeks ago
- Verilog library for ASIC and FPGA designers☆1,330Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆583Updated this week
- SERV - The SErial RISC-V CPU☆1,630Updated 2 months ago