RISC-V CPU Core (RV32IM)
☆1,719Sep 18, 2021Updated 4 years ago
Alternatives and similar repositories for riscv
Users that are interested in riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 32-bit Superscalar RISC-V CPU☆1,248Sep 18, 2021Updated 4 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,553May 12, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,149Jun 27, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,833Aug 6, 2025Updated 9 months ago
- Random instruction generator for RISC-V processor verification☆1,298Apr 3, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,142Feb 11, 2026Updated 3 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,939May 13, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,875May 7, 2026Updated 2 weeks ago
- Various HDL (Verilog) IP Cores☆902Jul 1, 2021Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,231Apr 17, 2026Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆981Nov 15, 2024Updated last year
- SERV - The SErial RISC-V CPU☆1,801Feb 19, 2026Updated 3 months ago
- VeeR EH1 core☆942May 29, 2023Updated 2 years ago
- A small, light weight, RISC CPU soft core☆1,540Dec 8, 2025Updated 5 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Basic RISC-V Test SoC☆193Apr 7, 2019Updated 7 years ago
- RISC-V Cores, SoC platforms and SoCs☆922Mar 26, 2021Updated 5 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆365Jan 12, 2018Updated 8 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,841Mar 24, 2021Updated 5 years ago
- Rocket Chip Generator☆3,773Apr 21, 2026Updated last month
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆234Aug 25, 2020Updated 5 years ago
- Verilog AXI components for FPGA implementation☆2,052Feb 27, 2025Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,161Mar 11, 2026Updated 2 months ago
- ☆1,189May 1, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,581May 15, 2026Updated last week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,061May 14, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,175Feb 21, 2026Updated 3 months ago
- A very simple and easy to understand RISC-V core.☆1,472Nov 9, 2023Updated 2 years ago
- RISC-V CPU Core☆428Jun 24, 2025Updated 10 months ago
- GNU toolchain for RISC-V, including GCC☆4,496Updated this week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆112Sep 18, 2021Updated 4 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆683Apr 16, 2026Updated last month
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆149Dec 2, 2019Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,074Apr 24, 2026Updated 3 weeks ago
- A DDR3 memory controller in Verilog for various FPGAs☆591Oct 10, 2021Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆803Apr 24, 2026Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆603May 7, 2026Updated 2 weeks ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆378Jul 12, 2017Updated 8 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆196May 16, 2026Updated last week
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆707Updated this week