Alternatives and similar repositories for riscv

Users that are interested in riscv are comparing it to the libraries listed below

• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,176Updated 4 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,725Updated 6 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,248Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,176Updated 8 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,751Updated last week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆909Updated 4 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,133Updated this week
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆1,049Updated this week
• riscv-software-src / riscv-tests
  ☆1,117Updated 2 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,487Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆922Updated 2 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,387Updated last year
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,999Updated last month
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,107Updated last year
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆962Updated last year
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,067Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,928Updated last year
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,485Updated last month
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,952Updated 11 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,504Updated 2 months ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,533Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆894Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,791Updated this week
• riscv-non-isa / riscv-arch-test
  ☆647Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆734Updated 5 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆766Updated 4 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆681Updated 6 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆653Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,746Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆603Updated last year