Alternatives and similar repositories for tree-core-ide

Users that are interested in tree-core-ide are comparing it to the libraries listed below

• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆171Updated 3 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆151Updated last year
• ljgibbslf / SM3_core
  ☆145Updated 5 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆76Updated 4 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆153Updated 2 months ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆172Updated last year
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆126Updated 3 years ago
• zion-group / VerilogCodingStyle
  ☆65Updated 5 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆53Updated 2 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆170Updated 2 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆78Updated 4 years ago
• BitOpenFPGA / arl
  lists of most popular repositories for most favoured programming languages (according to StackOverflow)
  ☆81Updated 5 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• ForrestBlue / cortexm0ds
  ☆74Updated 10 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆223Updated 5 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆39Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆124Updated 11 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆208Updated 5 months ago
• OpenXiangShan / XS-Verilog-Library
  ☆47Updated 3 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆96Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆94Updated 3 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆157Updated 2 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆74Updated 3 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 4 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆63Updated 4 years ago
• RV-BOSC / OpenNoC
  ☆220Updated 7 months ago
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆48Updated 4 years ago