Alternatives and similar repositories for tree-core-ide

Users that are interested in tree-core-ide are comparing it to the libraries listed below

• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆150Updated 2 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆136Updated 11 months ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆62Updated 2 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆147Updated 11 months ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆145Updated this week
• ljgibbslf / SM3_core
  ☆141Updated 4 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆120Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆114Updated 10 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆73Updated 3 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆72Updated 3 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆157Updated last year
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆154Updated 3 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆214Updated 4 years ago
• RV-BOSC / OpenNoC
  ☆158Updated last month
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆149Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆205Updated last year
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆111Updated 4 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆209Updated 10 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆100Updated last year
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆59Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆72Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆101Updated 3 years ago
• tastynoob / ritter-soc
  a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
  ☆23Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago