The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
☆113Sep 17, 2022Updated 3 years ago
Alternatives and similar repositories for tree-core-ide
Users that are interested in tree-core-ide are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Run rocket-chip on FPGA☆77Nov 16, 2025Updated 4 months ago
- The Ultra-Low Power RISC-V Core☆1,796Aug 6, 2025Updated 8 months ago
- The sources of the online SpinalHDL doc☆31Apr 4, 2026Updated last week
- Must-have verilog systemverilog modules☆1,948Mar 12, 2026Updated last month
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆372Jul 16, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- IC design and development should be faster，simpler and more reliable☆1,986Dec 31, 2021Updated 4 years ago
- Open-source high-performance RISC-V processor☆6,958Updated this week
- SpinalHDL documentation assets (pictures, slides, ...)☆32Dec 10, 2024Updated last year
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- Network components (NIC, Switch) for FireBox☆19Oct 27, 2024Updated last year
- A small, light weight, RISC CPU soft core☆1,533Dec 8, 2025Updated 4 months ago
- 常用Verilog模块☆20Mar 3, 2020Updated 6 years ago
- ☆10Apr 4, 2025Updated last year
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- GPGPU microprocessor architecture☆2,185Nov 8, 2024Updated last year
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,831Mar 24, 2021Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, A…☆47Nov 8, 2023Updated 2 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- This project is created and managed by EDA softwares, which contains the breeze quadcopter's component library, footprint library, schema…☆13Dec 15, 2017Updated 8 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- SPI-Flash XIP Interface (Verilog)☆49Oct 24, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Digital Logic Simulator☆35May 23, 2021Updated 4 years ago
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆5,367May 15, 2022Updated 3 years ago
- ☆32Mar 30, 2023Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 8 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,095Feb 11, 2026Updated 2 months ago
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- RISC-V YADAN Core, YADAN SoC, YADAN Board's Documentation, designed for engineering education. // 鸭蛋的文档。☆17Jan 16, 2025Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Dec 27, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Labs to learn SpinalHDL☆158Jul 4, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,873Mar 23, 2026Updated 2 weeks ago
- Library for MCP25625 click board☆10Jul 14, 2016Updated 9 years ago
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,527Jan 7, 2026Updated 3 months ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31May 18, 2019Updated 6 years ago