ultraembedded / biriscvLinks
32-bit Superscalar RISC-V CPU
☆1,053Updated 3 years ago
Alternatives and similar repositories for biriscv
Users that are interested in biriscv are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,086Updated last month
- RISC-V CPU Core (RV32IM)☆1,496Updated 3 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,575Updated last week
- Random instruction generator for RISC-V processor verification☆1,136Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,319Updated last week
- VeeR EH1 core☆884Updated 2 years ago
- Common SystemVerilog components☆634Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆924Updated 7 months ago
- RISC-V Cores, SoC platforms and SoCs☆893Updated 4 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆563Updated last week
- ☆1,033Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,611Updated last month
- ☆572Updated this week
- The OpenPiton Platform☆716Updated last month
- OpenXuantie - OpenC910 Core☆1,287Updated last year
- A Linux-capable RISC-V multicore for and by the world☆711Updated 2 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆668Updated 2 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,893Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆584Updated 11 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,048Updated 10 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆510Updated 5 months ago
- SystemVerilog to Verilog conversion☆645Updated 2 weeks ago
- educational microarchitectures for risc-v isa☆716Updated 4 months ago
- Digital Design with Chisel☆845Updated last week
- Verilog PCI express components☆1,377Updated last year
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆970Updated last week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆429Updated last month
- A small, light weight, RISC CPU soft core☆1,423Updated 5 months ago
- Verilog library for ASIC and FPGA designers☆1,309Updated last year
- Various HDL (Verilog) IP Cores☆818Updated 4 years ago