ultraembedded / biriscvLinks
32-bit Superscalar RISC-V CPU
☆1,086Updated 3 years ago
Alternatives and similar repositories for biriscv
Users that are interested in biriscv are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,109Updated 2 months ago
- RISC-V CPU Core (RV32IM)☆1,519Updated 3 years ago
- VeeR EH1 core☆889Updated 2 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,353Updated last week
- Random instruction generator for RISC-V processor verification☆1,153Updated 2 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,609Updated 2 weeks ago
- Functional verification project for the CORE-V family of RISC-V cores.☆583Updated this week
- Common SystemVerilog components☆649Updated this week
- RISC-V Cores, SoC platforms and SoCs☆895Updated 4 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆926Updated 9 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆984Updated last week
- A Linux-capable RISC-V multicore for and by the world☆721Updated this week
- ☆1,043Updated 2 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆588Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,937Updated this week
- OpenXuantie - OpenC910 Core☆1,300Updated last year
- ☆583Updated this week
- The OpenPiton Platform☆727Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆525Updated 2 weeks ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆509Updated 8 months ago
- SystemVerilog to Verilog conversion☆659Updated 2 months ago
- educational microarchitectures for risc-v isa☆719Updated 5 months ago
- The Ultra-Low Power RISC-V Core☆1,568Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆598Updated last week
- Digital Design with Chisel☆855Updated this week
- A small, light weight, RISC CPU soft core☆1,449Updated 2 weeks ago
- Verilog AXI components for FPGA implementation☆1,795Updated 5 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,058Updated 11 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆438Updated 3 months ago