ultraembedded / biriscvLinks
32-bit Superscalar RISC-V CPU
☆1,066Updated 3 years ago
Alternatives and similar repositories for biriscv
Users that are interested in biriscv are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,098Updated 2 months ago
- RISC-V CPU Core (RV32IM)☆1,507Updated 3 years ago
- Random instruction generator for RISC-V processor verification☆1,144Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,595Updated this week
- VeeR EH1 core☆885Updated 2 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,339Updated last week
- RISC-V Cores, SoC platforms and SoCs☆894Updated 4 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆925Updated 8 months ago
- ☆1,041Updated last month
- Common SystemVerilog components☆637Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆569Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆718Updated 3 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆978Updated 2 weeks ago
- ☆580Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,052Updated 10 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,915Updated this week
- OpenXuantie - OpenC910 Core☆1,296Updated last year
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆672Updated 2 weeks ago
- Simple RISC-V 3-stage Pipeline in Chisel☆586Updated 11 months ago
- The OpenPiton Platform☆721Updated last week
- SystemVerilog to Verilog conversion☆653Updated last month
- educational microarchitectures for risc-v isa☆718Updated 4 months ago
- Digital Design with Chisel☆852Updated last month
- The Ultra-Low Power RISC-V Core☆1,552Updated this week
- A small, light weight, RISC CPU soft core☆1,438Updated 5 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,834Updated 3 weeks ago
- Various HDL (Verilog) IP Cores☆820Updated 4 years ago
- SERV - The SErial RISC-V CPU☆1,615Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆512Updated 5 months ago
- An open-source static random access memory (SRAM) compiler.☆928Updated last month