ultraembedded / biriscvLinks
32-bit Superscalar RISC-V CPU
☆1,106Updated 4 years ago
Alternatives and similar repositories for biriscv
Users that are interested in biriscv are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,122Updated 4 months ago
- RISC-V CPU Core (RV32IM)☆1,554Updated 4 years ago
- Random instruction generator for RISC-V processor verification☆1,177Updated 3 weeks ago
- VeeR EH1 core☆900Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,646Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,385Updated last week
- RISC-V Cores, SoC platforms and SoCs☆897Updated 4 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆936Updated 11 months ago
- Common SystemVerilog components☆665Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆741Updated 2 weeks ago
- Functional verification project for the CORE-V family of RISC-V cores.☆602Updated last week
- OpenXuantie - OpenC910 Core☆1,331Updated last year
- The OpenPiton Platform☆732Updated 3 weeks ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆997Updated 2 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆673Updated 3 months ago
- ☆1,069Updated last week
- SERV - The SErial RISC-V CPU☆1,659Updated this week
- ☆598Updated last week
- Various HDL (Verilog) IP Cores☆839Updated 4 years ago
- Verilog PCI express components☆1,446Updated last year
- SystemVerilog to Verilog conversion☆670Updated 4 months ago
- The Ultra-Low Power RISC-V Core☆1,624Updated 2 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆595Updated last year
- A small, light weight, RISC CPU soft core☆1,465Updated 2 months ago
- educational microarchitectures for risc-v isa☆720Updated last month
- Digital Design with Chisel☆863Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,069Updated last year
- Verilog AXI components for FPGA implementation☆1,831Updated 7 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆515Updated 10 months ago