Alternatives and similar repositories for biriscv

Users that are interested in biriscv are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,080Updated 3 weeks ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,476Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆883Updated 2 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,568Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 2 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,308Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆627Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆708Updated last month
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆918Updated 7 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,600Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆556Updated 2 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆667Updated 3 weeks ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆966Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆639Updated last month
• riscv-software-src / riscv-tests
  ☆1,022Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆842Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆501Updated 4 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆581Updated 10 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆885Updated 4 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆710Updated last month
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated last month
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,517Updated 8 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆581Updated last week
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,281Updated 11 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆810Updated 3 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,042Updated 9 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,742Updated 3 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆911Updated 2 months ago