Alternatives and similar repositories for biriscv:

Users that are interested in biriscv are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,028Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,494Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆862Updated last year
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,398Updated 3 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,080Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated last week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,240Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated 3 weeks ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆710Updated 2 weeks ago
• riscv-software-src / riscv-tests
  ☆957Updated 3 weeks ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆919Updated 2 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,514Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆604Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆867Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆818Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆760Updated 3 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,368Updated last month
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,016Updated 6 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆506Updated this week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆563Updated 7 months ago
• riscv-non-isa / riscv-arch-test
  ☆549Updated this week
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,247Updated 10 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆673Updated 2 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆620Updated 2 weeks ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,792Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆426Updated 3 years ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,699Updated last month