XUANTIE-RV / openc910
OpenXuantie - OpenC910 Core
☆1,237Updated 8 months ago
Alternatives and similar repositories for openc910:
Users that are interested in openc910 are comparing it to the libraries listed below
- VeeR EH1 core☆862Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,028Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,792Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,494Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆972Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,441Updated 5 months ago
- Random instruction generator for RISC-V processor verification☆1,080Updated last month
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆919Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,240Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆904Updated 4 months ago
- RISC-V Cores, SoC platforms and SoCs☆867Updated 3 years ago
- educational microarchitectures for risc-v isa☆710Updated 2 weeks ago
- Digital Design with Chisel☆818Updated this week
- ☆957Updated 3 weeks ago
- Documentation for XiangShan☆408Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,847Updated this week
- OpenXuantie - OpenC906 Core☆343Updated 8 months ago
- RISC-V CPU Core (RV32IM)☆1,398Updated 3 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆563Updated 7 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,016Updated 6 months ago
- Various HDL (Verilog) IP Cores☆760Updated 3 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆484Updated 3 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆506Updated this week
- Verilog PCI express components☆1,247Updated 10 months ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,413Updated this week
- Verilog AXI components for FPGA implementation☆1,655Updated 3 weeks ago
- Common SystemVerilog components☆590Updated last week
- A template project for beginning new Chisel work☆623Updated last month
- The OpenPiton Platform☆673Updated 2 weeks ago
- A small, light weight, RISC CPU soft core☆1,368Updated last month