XUANTIE-RV / openc910
OpenXuantie - OpenC910 Core
☆1,166Updated 4 months ago
Related projects ⓘ
Alternatives and complementary repositories for openc910
- VeeR EH1 core☆822Updated last year
- The Ultra-Low Power RISC-V Core☆1,281Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,654Updated this week
- RISC-V Cores, SoC platforms and SoCs☆839Updated 3 years ago
- Random instruction generator for RISC-V processor verification☆1,026Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆966Updated 4 months ago
- 32-bit Superscalar RISC-V CPU☆865Updated 3 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,381Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,746Updated last month
- Digital Design with Chisel☆771Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,112Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆544Updated 3 months ago
- RISC-V CPU Core (RV32IM)☆1,272Updated 3 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆981Updated 2 months ago
- ☆898Updated this week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆850Updated 2 weeks ago
- Functional verification project for the CORE-V family of RISC-V cores.☆446Updated this week
- educational microarchitectures for risc-v isa☆688Updated 3 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆866Updated this week
- ☆516Updated last week
- A template project for beginning new Chisel work☆589Updated 5 months ago
- The OpenPiton Platform☆643Updated last month
- chisel tutorial exercises and answers☆696Updated 2 years ago
- Documentation for XiangShan☆351Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆452Updated 7 months ago
- Working Draft of the RISC-V Debug Specification Standard☆459Updated 2 months ago
- OpenXuantie - OpenC906 Core☆323Updated 4 months ago
- Source files for SiFive's Freedom platforms☆1,114Updated 3 years ago
- A small, light weight, RISC CPU soft core☆1,304Updated last month
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆631Updated this week