Alternatives and similar repositories for openc910

Users that are interested in openc910 are comparing it to the libraries listed below

• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆997Updated 2 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,106Updated 4 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆900Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,122Updated 4 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,624Updated 2 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆897Updated 4 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,177Updated 3 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,646Updated last month
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆936Updated 11 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,069Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆863Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,385Updated last week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,554Updated 4 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,999Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆595Updated last year
• riscv-software-src / riscv-tests
  ☆1,069Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆720Updated last month
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,981Updated 5 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆602Updated last week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆515Updated 10 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆664Updated last month
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆732Updated 3 weeks ago
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆371Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆665Updated 3 weeks ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆733Updated 3 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,446Updated last year
• riscv-non-isa / riscv-arch-test
  ☆598Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆741Updated 2 weeks ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆426Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,011Updated this week