Alternatives and similar repositories for vortex:

Users that are interested in vortex are comparing it to the libraries listed below

• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆917Updated 2 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,742Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆845Updated last year
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆678Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆666Updated 4 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆656Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆936Updated 3 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,215Updated 7 months ago
• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,044Updated 3 months ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,037Updated last month
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,806Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆801Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,468Updated 3 weeks ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆869Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,479Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,009Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,372Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆896Updated 3 months ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆897Updated 3 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,351Updated last week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆859Updated 3 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,063Updated last week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,198Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆570Updated last week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆906Updated last week
• VerticalResearchGroup / miaow
  An open source GPU based off of the AMD Southern Islands ISA.
  ☆1,118Updated 7 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆610Updated 7 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆559Updated 6 months ago
• riscv-software-src / riscv-tests
  ☆937Updated last week
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆998Updated 10 months ago