pulp-platform / redmuleLinks
☆88Updated last week
Alternatives and similar repositories for redmule
Users that are interested in redmule are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- The multi-core cluster of a PULP system.☆109Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆125Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆121Updated last month
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- ☆35Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆114Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆113Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated last month
- A DSL for Systolic Arrays☆82Updated 6 years ago
- ☆57Updated 7 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- PACoGen: Posit Arithmetic Core Generator☆74Updated 6 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- matrix-coprocessor for RISC-V☆25Updated 7 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Simple runtime for Pulp platforms☆49Updated 3 weeks ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆92Updated 10 months ago
- An open-source UCIe controller implementation☆76Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago