pulp-platform / redmule
☆36Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for redmule
- The multi-core cluster of a PULP system.☆56Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated last month
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆56Updated 2 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆36Updated last month
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆33Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆44Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- ☆21Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Chisel Cheatsheet☆31Updated last year
- ☆37Updated 5 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆32Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 6 months ago
- ☆25Updated 10 months ago
- Pulp virtual platform☆21Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆24Updated last month
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 8 months ago