GEMM and GEMM-Ops accelerator for PULP systems
☆120Sep 15, 2026Updated this week
Alternatives and similar repositories for redmule
Users that are interested in redmule are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆129Sep 7, 2026Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆173Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆240Updated this week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆120Nov 26, 2025Updated 9 months ago
- The multi-core cluster of a PULP system.☆116Aug 4, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An energy-efficient RISC-V floating-point compute cluster.☆148Aug 26, 2026Updated 3 weeks ago
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated last month
- A Fast, Low-Overhead On-chip Network☆346Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆367Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆101Aug 20, 2026Updated 3 weeks ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆39May 20, 2026Updated 3 months ago
- ☆37Sep 10, 2026Updated last week
- Open-source non-blocking L2 cache☆66Updated this week
- Common SystemVerilog components☆799Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A simple, scalable, source-synchronous, all-digital DDR link☆42Sep 1, 2026Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆119Sep 12, 2026Updated last week
- ☆51Updated this week
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆28Jan 6, 2026Updated 8 months ago
- ☆100Oct 18, 2023Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆548Aug 19, 2026Updated last month
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆26Updated this week
- A library to train and deploy quantised Deep Neural Networks☆28Dec 18, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago
- Chisel RISC-V Vector 1.0 Implementation☆158Sep 3, 2026Updated 2 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆162Oct 31, 2024Updated last year
- whatever it means☆19Jun 10, 2026Updated 3 months ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆17Aug 31, 2026Updated 2 weeks ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆300Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- CMake based hardware build system☆45Aug 31, 2026Updated 2 weeks ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- ☆19Jul 1, 2024Updated 2 years ago
- verilog实现CLAHE（限制对比度自适应直方图均衡化）算法，并进行资源优化，含vivado综合工程。 // Verilog implementation of CLAHE (Contrast Limited Adaptive Histogram…☆21Apr 30, 2026Updated 4 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆303Sep 12, 2026Updated last week
- Berkeley's Spatial Array Generator☆1,472Updated this week
- 简单的未优化的SRT除法器☆13Jun 16, 2024Updated 2 years ago