pulp-platform / redmuleLinks
☆90Updated this week
Alternatives and similar repositories for redmule
Users that are interested in redmule are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- The multi-core cluster of a PULP system.☆111Updated this week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆28Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- ☆37Updated last week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- matrix-coprocessor for RISC-V☆30Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- ☆58Updated 6 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆118Updated 2 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆123Updated 3 weeks ago
- ☆64Updated 9 months ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- RISC-V Matrix Specification☆23Updated last year
- Chisel Cheatsheet☆35Updated 2 years ago
- Next generation CGRA generator☆118Updated this week
- PACoGen: Posit Arithmetic Core Generator☆76Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- Advanced Architecture Labs with CVA6☆76Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago