chipsalliance / systemc-compilerLinks
Intel Compiler for SystemC
☆25Updated 2 years ago
Alternatives and similar repositories for systemc-compiler
Users that are interested in systemc-compiler are comparing it to the libraries listed below
Sorting:
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- ☆33Updated 8 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 10 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆45Updated 2 weeks ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Updated 5 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆88Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- ☆18Updated last week
- Chisel Cheatsheet☆34Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- A Rocket-based RISC-V superscalar in-order core☆36Updated last month
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- ☆30Updated 3 weeks ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- Simple UVM environment for experimenting with Verilator.☆28Updated 2 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Open source RTL simulation acceleration on commodity hardware☆32Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Open source process design kit for 28nm open process☆67Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago