Intel Compiler for SystemC
☆31Jun 1, 2023Updated 3 years ago
Alternatives and similar repositories for systemc-compiler
Users that are interested in systemc-compiler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆20Jan 29, 2026Updated 9 months ago
- SystemC Common Practices (SCP)☆41Feb 27, 2026Updated 8 months ago
- ☆27Oct 25, 2026Updated last week
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- OmniXtend cache coherence protocol☆85Jun 10, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆39Oct 22, 2026Updated last week
- MIDAS Public Release☆11Nov 27, 2018Updated 7 years ago
- RISC-V Functional ISA Simulator☆20May 28, 2026Updated 5 months ago
- BSC Development Workstation (BDW)☆34Oct 16, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆476Updated this week
- This is repo for the Niobium Compiler support in OpenFHE. It is up to date with OpenFHE 1.4.2☆15Updated this week
- A hardware compiler based on LLHD and CIRCT☆271Jun 30, 2025Updated last year
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 11 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- Simple UVM environment for experimenting with Verilator.☆55Sep 9, 2026Updated last month
- ☆30Oct 2, 2023Updated 3 years ago
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆43May 22, 2023Updated 3 years ago
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆68Updated this week
- (System)Verilog to Chisel translator☆125May 20, 2022Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆36Sep 30, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- PLL Simulator in SystemC-AMS☆11Oct 25, 2026Updated last week
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- ☆20Mar 1, 2021Updated 5 years ago
- UVM-SystemC reference implementation☆23Oct 9, 2026Updated 3 weeks ago
- ☆13Aug 22, 2022Updated 4 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 4 years ago
- ☆20Feb 25, 2026Updated 8 months ago
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated 2 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆320Sep 25, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- Algorithmic C Math Library☆68Oct 13, 2026Updated 2 weeks ago
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆25Updated this week
- ☆17Oct 16, 2026Updated 2 weeks ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Jan 14, 2018Updated 8 years ago
- ☆26Oct 14, 2026Updated 2 weeks ago
- Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python☆15Feb 3, 2021Updated 5 years ago