Alternatives and similar repositories for systemc-compiler

Users that are interested in systemc-compiler are comparing it to the libraries listed below

• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆113Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆66Updated 11 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 weeks ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆25Updated 6 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• pulp-platform / redmule
  ☆78Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆66Updated 3 weeks ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆43Updated 2 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆40Updated last week
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆30Updated 4 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆31Updated this week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆60Updated last week
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 4 months ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 9 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆16Updated 4 months ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆32Updated 5 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆114Updated last week