chipsalliance / systemc-compiler

Related projects ⓘ

Alternatives and complementary repositories for systemc-compiler

• pulp-platform / axi_llc
  ☆21Updated 2 months ago
• sequencer / arithmetic
  ☆31Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 2 weeks ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆47Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• chipsalliance / diplomacy
  ☆16Updated 4 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆40Updated this week
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆31Updated last year
• povik / yosys-slang
  slang-based frontend for Yosys
  ☆43Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆56Updated last week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆93Updated 7 months ago
• IObundle / iob-mem
  Verilog behavioral description of various memories
  ☆30Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated 3 weeks ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆30Updated last year
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆46Updated this week
• Xilinx / pcie-model
  PCI Express controller model
  ☆45Updated 2 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆27Updated 4 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆19Updated this week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆32Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆48Updated 2 weeks ago
• chipsalliance / fpga-interchange-schema
  ☆52Updated 2 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆31Updated last week
• TsaiAnson / verif
  ☆11Updated 3 years ago