Alternatives and similar repositories for systemc-compiler

Users that are interested in systemc-compiler are comparing it to the libraries listed below

• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆42Updated this week
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆32Updated 4 years ago
• pulp-platform / redmule
  ☆90Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆117Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 3 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆26Updated 7 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated 3 weeks ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆34Updated 2 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 3 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 4 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆35Updated 2 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated last week
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated this week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• samehattia / StateMover
  StateMover is a checkpoint-based debugging framework for FPGAs.
  ☆21Updated 3 years ago
• sequencer / arithmetic
  ☆33Updated 10 months ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆33Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago