Alternatives and similar repositories for FP-Gen

Users that are interested in FP-Gen are comparing it to the libraries listed below

• hyoukjun / microswitch-noc
  ☆29Updated 6 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• chipsalliance / aib-protocols
  ☆29Updated last year
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 4 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated last month
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆18Updated 11 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 6 years ago
• pulp-platform / hier-icache
  ☆14Updated 11 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆30Updated 3 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆28Updated 2 weeks ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆33Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 10 months ago
• pulp-platform / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆18Updated 2 months ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆21Updated 3 weeks ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• StanfordAHA / CGRAFlowDoc
  Documentation for the entire CGRAFlow
  ☆19Updated 4 years ago
• cornell-brg / pymtl-tutorial-isca2019
  Code for PyMTL Tutorial @ ISCA 2019
  ☆11Updated 6 years ago
• pulp-platform / ace
  ☆20Updated last month
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆28Updated 3 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆21Updated 3 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago
• pulp-platform / apb
  APB Logic
  ☆23Updated 2 weeks ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• PacoReinaCampo / MPSoC-RISCV
  Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆13Updated this week
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆15Updated 11 years ago