StanfordVLSI / FP-Gen
FPU Generator
☆20Updated 3 years ago
Alternatives and similar repositories for FP-Gen:
Users that are interested in FP-Gen are comparing it to the libraries listed below
- ☆25Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated last year
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Open Source PHY v2☆27Updated 11 months ago
- ☆26Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆25Updated this week
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- DASS HLS Compiler☆29Updated last year
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Updated 7 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- ☆13Updated last month
- Project repo for the POSH on-chip network generator☆45Updated 2 weeks ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆18Updated 11 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- CNN accelerator☆28Updated 7 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago