pulp-platform / ITALinks
☆61Updated 8 months ago
Alternatives and similar repositories for ITA
Users that are interested in ITA are comparing it to the libraries listed below
Sorting:
- ☆57Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆75Updated last month
- eyeriss-chisel3☆40Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆77Updated 4 months ago
- ☆39Updated 6 years ago
- matrix-coprocessor for RISC-V☆26Updated 2 weeks ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆29Updated 3 months ago
- ☆37Updated 2 months ago
- ☆89Updated last week
- HLS for Networks-on-Chip☆38Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆101Updated 2 weeks ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- ☆19Updated 7 months ago
- ☆71Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- An open-source UCIe controller implementation☆80Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆133Updated 10 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆205Updated 5 years ago
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆39Updated last week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆158Updated 9 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆71Updated 5 years ago
- ☆12Updated 2 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆35Updated 2 years ago