pulp-platform / ITA

Related projects ⓘ

Alternatives and complementary repositories for ITA

• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆23Updated last month
• pulp-platform / fpu
  ☆37Updated 5 years ago
• AsFigo / MathLib
  MathLib DAC 2023 version
  ☆12Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆30Updated last year
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆10Updated last month
• hyoukjun / microswitch-noc
  ☆22Updated 5 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆44Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆32Updated 3 weeks ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆12Updated 9 months ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆19Updated 3 weeks ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆22Updated 3 months ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• pulp-platform / axi_llc
  ☆20Updated 2 months ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated 2 weeks ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• msyksphinz-self / riscv-vector-tests
  Original test vector of RISC-V Vector Extension
  ☆11Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆22Updated last month
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated 3 weeks ago
• ym31433 / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆18Updated 7 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆47Updated 4 months ago
• Nikola2444 / RISC-V-vector-processor
  ☆10Updated 2 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆12Updated 3 years ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆18Updated last month
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆25Updated 5 months ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆36Updated 5 months ago
• KULeuven-MICAS / tinyvers
  TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.
  ☆12Updated last year
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆25Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago