☆79Apr 22, 2025Updated last year
Alternatives and similar repositories for ITA
Users that are interested in ITA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆24Apr 17, 2026Updated 3 months ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆186Apr 15, 2026Updated 3 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆264Mar 24, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- DNN Compiler for Heterogeneous SoCs☆71Jun 23, 2026Updated 3 weeks ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆107Nov 26, 2025Updated 7 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆38Oct 23, 2025Updated 8 months ago
- ☆27Jan 30, 2026Updated 5 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆39Aug 13, 2024Updated last year
- Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of…☆17Mar 30, 2025Updated last year
- ☆19Jul 9, 2026Updated last week
- Spike with a coherence supported cache model☆14Jul 9, 2024Updated 2 years ago
- Research and Materials on Hardware implementation of Transformer Model☆309Feb 28, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆151Jan 20, 2025Updated last year
- GEMM and GEMM-Ops accelerator for PULP systems☆108Updated this week
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆209Jan 8, 2026Updated 6 months ago
- 这是一个用chisel实现的FP8混合乘加单元☆18Jun 18, 2025Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆34May 17, 2026Updated 2 months ago
- matrix-coprocessor for RISC-V☆36Feb 27, 2026Updated 4 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆26Jul 2, 2026Updated 2 weeks ago
- The official NaplesPU hardware code repository☆35Jul 27, 2019Updated 6 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆136Aug 27, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- ☆41Oct 12, 2025Updated 9 months ago
- IC implementation of Systolic Array for TPU☆366Oct 21, 2024Updated last year
- A reliable, real-time subsystem for the Carfield SoC☆21Dec 2, 2025Updated 7 months ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆15Jun 25, 2025Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- ☆21Nov 23, 2022Updated 3 years ago
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆30Dec 18, 2024Updated last year
- FPGA based Vision Transformer accelerator (Harvard CS205)☆160Feb 11, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Jun 4, 2024Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆55Jan 2, 2025Updated last year
- ☆43Updated this week
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 9 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆20Jun 18, 2026Updated last month
- FPGA systolic array AI engine☆37Jan 2, 2026Updated 6 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago