☆67Apr 22, 2025Updated 11 months ago
Alternatives and similar repositories for ITA
Users that are interested in ITA are comparing it to the libraries listed below
Sorting:
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆58Nov 22, 2023Updated 2 years ago
- DNN Compiler for Heterogeneous SoCs☆63Updated this week
- ☆19Oct 7, 2025Updated 5 months ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆191Jan 8, 2026Updated 2 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- ☆14Mar 9, 2026Updated last week
- A reliable, real-time subsystem for the Carfield SoC☆20Dec 2, 2025Updated 3 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- ☆23Mar 12, 2026Updated last week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 3 weeks ago
- ☆10Jun 4, 2024Updated last year
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- ☆97Mar 5, 2026Updated 2 weeks ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Mar 7, 2024Updated 2 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 4 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆32Mar 4, 2026Updated 2 weeks ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- A library to train and deploy quantised Deep Neural Networks☆27Dec 18, 2024Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆234Mar 24, 2024Updated last year
- A Toy-Purpose TPU Simulator☆22Jun 7, 2024Updated last year
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 4 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- ☆82Feb 2, 2026Updated last month
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- ☆27Feb 27, 2025Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- ☆14Jun 22, 2022Updated 3 years ago
- Administrative repository for the Integrated Matrix Extension Task Group☆34Dec 15, 2025Updated 3 months ago