semidynamics / OpenVectorInterfaceLinks
Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
☆37Updated 3 years ago
Alternatives and similar repositories for OpenVectorInterface
Users that are interested in OpenVectorInterface are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆112Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated 11 months ago
- ☆76Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆66Updated 2 weeks ago
- The multi-core cluster of a PULP system.☆108Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 months ago
- The specification for the FIRRTL language☆63Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated last month
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆108Updated 2 years ago
- RISC-V Virtual Prototype☆177Updated 9 months ago
- ☆90Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- A modeling library with virtual components for SystemC and TLM simulators☆168Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- RISC-V Verification Interface☆107Updated last week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆117Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated this week
- ☆85Updated 3 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Pure digital components of a UCIe controller☆71Updated 3 weeks ago
- ☆57Updated 2 weeks ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated 2 weeks ago
- ☆80Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆58Updated 2 years ago