pulp-platform / spatzLinks
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
☆134Updated this week
Alternatives and similar repositories for spatz
Users that are interested in spatz are comparing it to the libraries listed below
Sorting:
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆190Updated 3 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆121Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆126Updated 3 months ago
- The multi-core cluster of a PULP system.☆111Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- A Fast, Low-Overhead On-chip Network☆259Updated 3 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated this week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆233Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆76Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- ☆72Updated 3 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Unit tests generator for RVV 1.0☆99Updated 2 months ago
- ☆90Updated 3 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆313Updated last week
- Vector processor for RISC-V vector ISA☆134Updated 5 years ago
- Generic Register Interface (contains various adapters)☆134Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Updated last year
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆116Updated 5 months ago
- ☆150Updated 2 years ago
- ☆121Updated 5 months ago
- high-performance RTL simulator☆185Updated last year
- Self checking RISC-V directed tests☆118Updated 7 months ago
- ☆192Updated 2 years ago
- RISC-V Verification Interface☆136Updated last month
- Open-source RTL logic simulator with CUDA acceleration☆249Updated 3 months ago
- RISC-V Virtual Prototype☆183Updated last year
- Simple runtime for Pulp platforms☆50Updated 2 months ago