Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
☆159Jun 23, 2026Updated this week
Alternatives and similar repositories for spatz
Users that are interested in spatz are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Rocket-based RISC-V superscalar in-order core☆41Jun 14, 2026Updated 2 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆346Updated this week
- The multi-core cluster of a PULP system.☆114Jun 19, 2026Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆526Jun 8, 2026Updated 3 weeks ago
- An energy-efficient RISC-V floating-point compute cluster.☆137Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆321Updated this week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆127Jun 11, 2026Updated 2 weeks ago
- ☆109Jun 17, 2026Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆219Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆150Apr 23, 2026Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆108May 22, 2026Updated last month
- A reliable, real-time subsystem for the Carfield SoC☆20Dec 2, 2025Updated 6 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆92Updated this week
- A Fast, Low-Overhead On-chip Network☆313Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆230Nov 22, 2023Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆183Apr 1, 2026Updated 2 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆152Jun 11, 2026Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆617May 26, 2026Updated last month
- ☆25Jun 23, 2024Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆32May 20, 2026Updated last month
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆550Jun 22, 2026Updated last week
- Self checking RISC-V directed tests☆124Jun 3, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Tile based architecture designed for computing efficiency, scalability and generality☆299Jun 16, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,182Feb 21, 2026Updated 4 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆106Updated this week
- Common SystemVerilog components☆762Updated this week
- RISC-V Matrix Specification☆26Dec 2, 2024Updated last year
- 32-bit Superscalar RISC-V CPU☆1,266Sep 18, 2021Updated 4 years ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆276Jun 16, 2026Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆26Jan 6, 2026Updated 5 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆133Jul 11, 2025Updated 11 months ago
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆244May 12, 2026Updated last month
- RISC-V Zve32x Vector Coprocessor☆220Jan 22, 2026Updated 5 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆273Nov 6, 2024Updated last year
- ☆62Mar 31, 2025Updated last year
- ☆40Updated this week