Alternatives and similar repositories for spatz

Users that are interested in spatz are comparing it to the libraries listed below

• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆105Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆169Updated 3 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆86Updated last week
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆91Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆62Updated 5 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆103Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆111Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated 2 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆65Updated 2 months ago
• bsc-loca / sargantana
  ☆105Updated last month
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆110Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆69Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆214Updated last week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆167Updated this week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆121Updated 4 years ago
• pulp-platform / redmule
  ☆68Updated this week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆180Updated 2 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated 3 weeks ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆271Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆262Updated 3 weeks ago
• tenstorrent / whisper
  ☆47Updated last month
• chipsalliance / uvm-verilator
  ☆96Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆97Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆123Updated last month
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 4 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆142Updated last month
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 2 months ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆201Updated 2 weeks ago