pulp-platform / carfield
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
☆73Updated this week
Related projects ⓘ
Alternatives and complementary repositories for carfield
- The multi-core cluster of a PULP system.☆56Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 5 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- Generic Register Interface (contains various adapters)☆100Updated last month
- Simple runtime for Pulp platforms☆36Updated last week
- ☆75Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆131Updated 3 weeks ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆169Updated 10 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- A SystemVerilog source file pickler.☆51Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆56Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆199Updated this week
- RISC-V System on Chip Template☆153Updated this week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆80Updated 2 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- RISC-V Verification Interface☆76Updated 2 months ago
- Fabric generator and CAD tools☆148Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆216Updated 2 weeks ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆110Updated 4 months ago
- ☆122Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆195Updated 2 weeks ago