A simple, scalable, source-synchronous, all-digital DDR link
☆36Mar 13, 2026Updated last week
Alternatives and similar repositories for serial_link
Users that are interested in serial_link are comparing it to the libraries listed below
Sorting:
- ☆36Dec 22, 2025Updated 2 months ago
- ☆34Feb 17, 2026Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆202Mar 6, 2026Updated 2 weeks ago
- ☆16Oct 20, 2025Updated 5 months ago
- ☆17Oct 28, 2025Updated 4 months ago
- ☆59Mar 31, 2025Updated 11 months ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆23Jan 6, 2026Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆272Mar 13, 2026Updated last week
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Nov 12, 2025Updated 4 months ago
- A reliable, real-time subsystem for the Carfield SoC☆19Dec 2, 2025Updated 3 months ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- ☆21Mar 11, 2026Updated last week
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated last week
- Common SystemVerilog components☆723Mar 11, 2026Updated last week
- ☆13May 5, 2023Updated 2 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- ☆96Mar 5, 2026Updated 2 weeks ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆239Jul 16, 2023Updated 2 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- Tiny C Compiler for AVR architecture☆13Nov 19, 2017Updated 8 years ago
- ☆19Oct 7, 2025Updated 5 months ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 7 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Jan 8, 2019Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,519Mar 11, 2026Updated last week
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Sata 2 Host Controller for FPGA implementation☆18Oct 11, 2017Updated 8 years ago
- ☆30Jul 9, 2025Updated 8 months ago
- A SystemVerilog source file pickler.☆60Oct 20, 2024Updated last year
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆12Aug 21, 2023Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆48Oct 24, 2021Updated 4 years ago
- Intel Compiler for SystemC☆29Jun 1, 2023Updated 2 years ago