pulp-platform / serial_link
A simple, scalable, source-synchronous, all-digital DDR link
☆25Updated this week
Alternatives and similar repositories for serial_link:
Users that are interested in serial_link are comparing it to the libraries listed below
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- ☆27Updated 3 weeks ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆13Updated last week
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Network on Chip for MPSoC☆26Updated last week
- ☆25Updated 3 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆25Updated 10 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- ☆23Updated 3 weeks ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- ☆55Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆29Updated this week
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- verification of simple axi-based cache☆18Updated 5 years ago
- AXI X-Bar☆19Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- ☆20Updated 5 years ago
- SoC Based on ARM Cortex-M3☆30Updated this week
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 7 months ago