bsc-loca / sauriaLinks
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
☆77Updated last month
Alternatives and similar repositories for sauria
Users that are interested in sauria are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆39Updated 4 years ago
- ☆40Updated 6 years ago
- ☆28Updated 6 years ago
- Template for project1 TPU☆21Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- ☆57Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- ☆61Updated 8 months ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- ☆65Updated 8 months ago
- ☆38Updated 2 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- ☆72Updated 7 years ago
- ☆19Updated 8 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆102Updated last week
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆30Updated 4 months ago
- Public release☆58Updated 6 years ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- ☆67Updated 3 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆71Updated 5 months ago
- ☆31Updated 5 years ago