bsc-loca / sauria
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
☆37Updated 6 months ago
Alternatives and similar repositories for sauria:
Users that are interested in sauria are comparing it to the libraries listed below
- ☆26Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆25Updated last year
- ☆31Updated 5 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- ☆3Updated 3 years ago
- Template for project1 TPU☆18Updated 3 years ago
- ☆43Updated 6 years ago
- ☆13Updated 9 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆73Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆59Updated last year
- eyeriss-chisel3☆40Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆18Updated last year
- ☆26Updated 4 years ago
- ☆8Updated last year
- Reconfigurable Binary Engine☆16Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆52Updated 3 years ago
- ☆35Updated 2 weeks ago