Alternatives and similar repositories for sauria

Users that are interested in sauria are comparing it to the libraries listed below

• hyoukjun / microswitch-noc
  ☆28Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆39Updated 6 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆73Updated 5 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆38Updated 4 years ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 2 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆21Updated 4 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆60Updated last week
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆78Updated 7 years ago
• pulp-platform / ITA
  ☆60Updated 8 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 7 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆71Updated 5 years ago
• VeriGOOD-ML / public
  ☆65Updated 7 months ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆35Updated 2 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆100Updated last week
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆37Updated 2 months ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆33Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 9 months ago
• gem5-X / TiC-SAT
  ☆19Updated 7 months ago
• vaughnbetz / COFFE
  ☆46Updated last year
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆32Updated 2 years ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆70Updated 5 months ago
• mcjtag / bitonic_sorter
  Bitonic sorter (Batcher's sorting network) written in Verilog.
  ☆35Updated last year