bsc-loca / sauria
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
☆40Updated 7 months ago
Alternatives and similar repositories for sauria:
Users that are interested in sauria are comparing it to the libraries listed below
- ☆26Updated 5 years ago
- ☆32Updated 6 years ago
- ☆3Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Template for project1 TPU☆18Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- ☆15Updated 10 months ago
- ☆42Updated last week
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆17Updated last year
- ☆46Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆27Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆45Updated 2 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆35Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- ☆27Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- SRAM☆22Updated 4 years ago
- ☆59Updated this week
- ☆25Updated last year