bsc-loca / sauria
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
☆23Updated last month
Related projects ⓘ
Alternatives and complementary repositories for sauria
- ☆10Updated 5 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆22Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆17Updated 11 months ago
- ☆26Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆19Updated last year
- ☆8Updated last year
- ☆37Updated 5 years ago
- ☆21Updated last month
- HLS for Networks-on-Chip☆31Updated 3 years ago
- sram/rram/mram.. compiler☆29Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- ☆3Updated 3 years ago
- NPUsim: Full-system, Cycle-accurate, Value-aware NPU Simulator☆24Updated last week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆24Updated 3 years ago
- ☆33Updated 3 years ago
- ☆25Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- course design☆21Updated 6 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆21Updated 5 years ago
- Ratatoskr NoC Simulator☆21Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- ☆12Updated this week
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago