kimianoorbakhsh / Verilog-Matrix-MultiplierLinks
Final Project for Digital Systems Design Course, Fall 2020
☆17Updated 3 years ago
Alternatives and similar repositories for Verilog-Matrix-Multiplier
Users that are interested in Verilog-Matrix-Multiplier are comparing it to the libraries listed below
Sorting:
- Design and UVM-TB of RISC -V Microprocessor☆33Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆15Updated 3 years ago
- ☆14Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆40Updated 6 years ago
- ☆15Updated 3 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated last year
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- ☆31Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆20Updated 10 months ago
- EE577b-Course-Project☆19Updated 5 years ago
- ☆18Updated 10 years ago
- ☆20Updated 3 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆56Updated 5 years ago
- Formal Verification of RISC V IM Processor☆10Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Updated 6 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆23Updated 10 months ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆32Updated 11 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Updated 2 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆38Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 13 years ago
- The memory model was leveraged from micron.☆27Updated 7 years ago