kimianoorbakhsh / Verilog-Matrix-MultiplierLinks
Final Project for Digital Systems Design Course, Fall 2020
☆12Updated 2 years ago
Alternatives and similar repositories for Verilog-Matrix-Multiplier
Users that are interested in Verilog-Matrix-Multiplier are comparing it to the libraries listed below
Sorting:
- verification of simple axi-based cache☆18Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- ☆20Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆20Updated 11 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆28Updated 4 years ago
- ☆33Updated 6 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 4 years ago
- ☆14Updated 2 years ago
- ☆14Updated 2 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- AXI Interconnect☆49Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆14Updated 7 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- ☆27Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆17Updated 10 years ago
- Two Level Cache Controller implementation in Verilog HDL☆48Updated 4 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆20Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆49Updated 6 years ago