Open-source AI acceleration on FPGA: from ONNX to RTL
☆49Jan 5, 2026Updated last month
Alternatives and similar repositories for brainsmith
Users that are interested in brainsmith are comparing it to the libraries listed below
Sorting:
- Using e-graphs for logic synthesis (ICCAD'25)☆32Feb 20, 2026Updated last week
- Large-scale medical image processing and reconstruction toolbox☆18Feb 13, 2024Updated 2 years ago
- An open-source Simulation Trace Format specification☆15Nov 12, 2025Updated 3 months ago
- A research shell for Alveo V80☆25Dec 17, 2025Updated 2 months ago
- ☆17Feb 3, 2023Updated 3 years ago
- ☆27Mar 31, 2025Updated 11 months ago
- ☆17Mar 26, 2025Updated 11 months ago
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆15Updated this week
- Synthesize Verilog to Minecraft redstone☆21Nov 9, 2024Updated last year
- ☆19Jul 12, 2024Updated last year
- A fast and certifying solver for quantified Boolean formulas.☆26Apr 29, 2025Updated 10 months ago
- ☆21Jun 23, 2024Updated last year
- FINN+ is an extended version of FINN, a dataflow compiler for QNN inference on FPGAs. It is maintained by a group of researchers at Pader…☆39Feb 22, 2026Updated last week
- Serpens is an HBM FPGA accelerator for SpMV☆22Jul 26, 2024Updated last year
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Tiny verified SAT-solver☆30Jan 7, 2022Updated 4 years ago
- CMake based hardware build system☆35Feb 16, 2026Updated last week
- 🔭 interactively explore `onnx` networks in your CLI.☆26Jun 7, 2024Updated last year
- Codebase for ICML'24 paper: Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs☆27Jun 25, 2024Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Dec 19, 2025Updated 2 months ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Mar 5, 2025Updated 11 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- A tool to generate optimized hardware files for univariate functions.☆29Apr 5, 2024Updated last year
- design and verification of asynchronous circuits☆43Jan 18, 2026Updated last month
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆166Updated this week
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆88Feb 13, 2026Updated 2 weeks ago
- Pick your favorite language to verify your chip.☆77Jan 30, 2026Updated last month
- A design automation framework to engineer decision diagrams yourself☆26Updated this week
- ☆40Jan 22, 2026Updated last month
- ☆91Feb 19, 2026Updated last week
- Allo Accelerator Design and Programming Framework (PLDI'24)☆352Feb 8, 2026Updated 2 weeks ago
- UB-aware interpreter for LLVM debugging☆44Feb 13, 2026Updated 2 weeks ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- 21st century electronic design automation tools, written in Rust.☆36Feb 20, 2026Updated last week
- This is a Login application for Android using Parse server.☆10Nov 26, 2018Updated 7 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Feb 22, 2026Updated last week
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated 3 weeks ago