microsoft / brainsmithLinks
Open-source AI acceleration on FPGA: from ONNX to RTL
☆38Updated last week
Alternatives and similar repositories for brainsmith
Users that are interested in brainsmith are comparing it to the libraries listed below
Sorting:
- Using e-graphs for logic synthesis☆28Updated this week
- ☆17Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆34Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated 8 months ago
- ☆53Updated 5 months ago
- ☆60Updated 8 months ago
- ☆17Updated 8 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆52Updated 2 years ago
- ☆17Updated 4 months ago
- CGRA framework with vectorization support.☆41Updated last week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated this week
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- ☆65Updated 7 months ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆56Updated 4 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- A hardware synthesis framework with multi-level paradigm☆42Updated 11 months ago
- A research shell for Alveo V80☆19Updated this week
- ☆62Updated this week
- ☆16Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- ☆32Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- An Open-Source Tool for CGRA Accelerators☆79Updated 3 months ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago