Alternatives and similar repositories for iDMA

Users that are interested in iDMA are comparing it to the libraries listed below

• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆134Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆259Updated 3 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆134Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆189Updated last week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆134Updated 5 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆76Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆136Updated last month
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated this week
• pulp-platform / redmule
  ☆90Updated 3 weeks ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆196Updated 3 years ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆121Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆160Updated 4 months ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆233Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆79Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆116Updated 5 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆313Updated this week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆201Updated 4 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆144Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆252Updated last year
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆145Updated last year
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆50Updated 2 months ago
• ucb-bar / uciedigital
  An open-source UCIe controller implementation
  ☆81Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆126Updated 3 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 10 months ago