A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
☆196Updated this week
Alternatives and similar repositories for iDMA
Users that are interested in iDMA are comparing it to the libraries listed below
Sorting:
- Generic Register Interface (contains various adapters)☆136Feb 14, 2026Updated 2 weeks ago
- The multi-core cluster of a PULP system.☆111Feb 2, 2026Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- ☆93Updated this week
- A Fast, Low-Overhead On-chip Network☆269Updated this week
- Common SystemVerilog components☆713Updated this week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆119Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆318Feb 20, 2026Updated last week
- ☆14Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,500Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆138Updated this week
- ☆34Feb 17, 2026Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆295Feb 4, 2026Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆490Nov 27, 2025Updated 3 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆36Dec 8, 2025Updated 2 months ago
- General Purpose AXI Direct Memory Access☆62May 12, 2024Updated last year
- Simple runtime for Pulp platforms☆51Feb 2, 2026Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated 3 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆155Oct 31, 2024Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆210Feb 21, 2026Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆258Nov 6, 2024Updated last year
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆313Feb 11, 2026Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆101Feb 20, 2026Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆279Feb 20, 2026Updated last week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37May 4, 2024Updated last year
- Opensource DDR3 Controller☆418Jan 18, 2026Updated last month
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆112Sep 24, 2025Updated 5 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated this week
- pulp_soc is the core building component of PULP based SoCs☆82Mar 10, 2025Updated 11 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆661Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆570Oct 21, 2025Updated 4 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆461May 15, 2025Updated 9 months ago
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 2 weeks ago
- Verilog Configurable Cache☆192Feb 17, 2026Updated last week
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆335Dec 11, 2024Updated last year
- Verilog library for ASIC and FPGA designers☆1,392May 8, 2024Updated last year