pulp-platform / iDMALinks
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
☆174Updated last month
Alternatives and similar repositories for iDMA
Users that are interested in iDMA are comparing it to the libraries listed below
Sorting:
- The multi-core cluster of a PULP system.☆106Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- A Fast, Low-Overhead On-chip Network☆221Updated 3 weeks ago
- Verilog Configurable Cache☆181Updated 8 months ago
- Generic Register Interface (contains various adapters)☆126Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated this week
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- RISC-V System on Chip Template☆159Updated last week
- RISC-V Verification Interface☆100Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- An energy-efficient RISC-V floating-point compute cluster.☆99Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆278Updated this week
- Simple runtime for Pulp platforms☆48Updated last week
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated last year
- Open-source high-performance non-blocking cache☆87Updated 3 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated 2 months ago
- ☆97Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆169Updated this week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆101Updated 3 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆173Updated 9 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆210Updated 3 weeks ago
- Network on Chip Implementation written in SytemVerilog☆188Updated 2 years ago