pulp-platform / iDMA
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
☆137Updated 2 weeks ago
Alternatives and similar repositories for iDMA:
Users that are interested in iDMA are comparing it to the libraries listed below
- A Fast, Low-Overhead On-chip Network☆182Updated this week
- Generic Register Interface (contains various adapters)☆111Updated 5 months ago
- Verilog Configurable Cache☆174Updated 3 months ago
- The multi-core cluster of a PULP system.☆85Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated last week
- ☆88Updated last year
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- Vector processor for RISC-V vector ISA☆116Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- RISC-V Verification Interface☆85Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆99Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 4 months ago
- Pure digital components of a UCIe controller☆56Updated this week
- An AXI4 crossbar implementation in SystemVerilog☆137Updated last month
- PCI express simulation framework for Cocotb☆153Updated last year
- A dynamic verification library for Chisel.☆146Updated 4 months ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- ☆53Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- RISC-V System on Chip Template☆156Updated this week
- An Open-Source Design and Verification Environment for RISC-V☆79Updated 3 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 10 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆63Updated 9 months ago
- A Chisel RTL generator for network-on-chip interconnects☆186Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆249Updated 2 weeks ago
- Various caches written in Verilog-HDL☆117Updated 9 years ago