Alternatives and similar repositories for iDMA

Users that are interested in iDMA are comparing it to the libraries listed below

• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆231Updated last week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆92Updated 2 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated 3 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆184Updated 2 weeks ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆130Updated last week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆67Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆122Updated 2 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆108Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆112Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆129Updated 5 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆217Updated this week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆291Updated last week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆142Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆113Updated this week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆215Updated 2 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆85Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• chipsalliance / uvm-verilator
  ☆99Updated 2 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆269Updated last month
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆192Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆176Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 11 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• pulp-platform / redmule
  ☆80Updated last week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 7 months ago