A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
☆202Mar 6, 2026Updated last month
Alternatives and similar repositories for iDMA
Users that are interested in iDMA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated last month
- A Fast, Low-Overhead On-chip Network☆277Apr 2, 2026Updated last week
- The multi-core cluster of a PULP system.☆113Mar 28, 2026Updated last week
- ☆97Mar 5, 2026Updated last month
- ☆15Mar 9, 2026Updated last month
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Common SystemVerilog components☆727Mar 31, 2026Updated last week
- ☆34Feb 17, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆129Jul 11, 2025Updated 8 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,539Mar 31, 2026Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆325Apr 2, 2026Updated last week
- A simple, scalable, source-synchronous, all-digital DDR link☆37Apr 1, 2026Updated last week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆126Apr 1, 2026Updated last week
- General Purpose AXI Direct Memory Access☆65May 12, 2024Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆305Apr 1, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆23Jan 6, 2026Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆143Updated this week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆117Sep 24, 2025Updated 6 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆507Apr 3, 2026Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆219Mar 25, 2026Updated 2 weeks ago
- ☆36Dec 22, 2025Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆102Mar 19, 2026Updated 3 weeks ago
- Opensource DDR3 Controller☆425Jan 18, 2026Updated 2 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆267Nov 6, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- RISC-V IOMMU Demo (Linux & Bao)☆24Dec 5, 2023Updated 2 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆126Mar 13, 2026Updated 3 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆38May 4, 2024Updated last year
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated 2 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆470May 15, 2025Updated 10 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆157Oct 31, 2024Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆84Feb 5, 2026Updated 2 months ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆315Mar 31, 2026Updated last week
- A dependency management tool for hardware projects.☆360Apr 2, 2026Updated last week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Tile based architecture designed for computing efficiency, scalability and generality☆286Mar 30, 2026Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆587Updated this week
- AIA IP compliant with the RISC-V AIA spec☆46Jan 27, 2025Updated last year
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆19Oct 23, 2023Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆657Apr 3, 2026Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆543Nov 26, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆790Updated this week