☆16May 6, 2026Updated 3 months ago
Alternatives and similar repositories for pulp-ethernet
Users that are interested in pulp-ethernet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆226Updated this week
- ☆25Apr 17, 2026Updated 3 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Generic Register Interface (contains various adapters)☆141Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V fast interrupt controller☆35Updated this week
- whatever it means☆18Jun 10, 2026Updated 2 months ago
- SGMII☆14Jul 17, 2014Updated 12 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- ☆38Jul 23, 2026Updated 2 weeks ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆23Updated this week
- Wishbone SATA Controller☆28Jul 9, 2026Updated last month
- Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.☆24Dec 11, 2025Updated 7 months ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A simple, scalable, source-synchronous, all-digital DDR link☆39Updated this week
- A Fast, Low-Overhead On-chip Network☆325Aug 3, 2026Updated last week
- A framework for ysyx flow☆14Oct 31, 2024Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆22Apr 30, 2019Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆107Jan 27, 2024Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆111Jul 28, 2026Updated last week
- The multi-core cluster of a PULP system.☆114Updated this week
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆42Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Jul 10, 2026Updated last month
- 1G eth UDP / IP Stack☆10Jul 17, 2014Updated 12 years ago
- USB -> AXI Debug Bridge☆46Jun 5, 2021Updated 5 years ago
- An 8b10b decoder and encoder in logic in VHDL☆26Apr 12, 2021Updated 5 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆154Mar 17, 2023Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Jul 23, 2026Updated 2 weeks ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆264Updated this week
- Superscalar Out-of-Order NPU Design on FPGA☆16May 17, 2024Updated 2 years ago
- Tensor Processing Unit implementation in Verilog☆15Mar 18, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- uvm_starter is a simple template for starting uvm projects☆12Feb 11, 2025Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆91Apr 1, 2026Updated 4 months ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆18Jul 31, 2026Updated last week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆67Jul 17, 2026Updated 3 weeks ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆39Oct 29, 2023Updated 2 years ago