☆16Oct 5, 2026Updated this week
Alternatives and similar repositories for pulp-ethernet
Users that are interested in pulp-ethernet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆246Updated this week
- ☆28Apr 17, 2026Updated 5 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated 2 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- RISC-V fast interrupt controller☆35Aug 6, 2026Updated 2 months ago
- SGMII☆14Jul 17, 2014Updated 12 years ago
- whatever it means☆19Jun 10, 2026Updated 3 months ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- ☆40Sep 30, 2026Updated last week
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆24Sep 10, 2026Updated 3 weeks ago
- Wishbone SATA Controller☆28Sep 17, 2026Updated 3 weeks ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆42Oct 1, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.☆26Dec 11, 2025Updated 9 months ago
- A framework for ysyx flow☆14Oct 31, 2024Updated last year
- A Fast, Low-Overhead On-chip Network☆358Updated this week
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆22Apr 30, 2019Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆108Jan 27, 2024Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆119Sep 12, 2026Updated 3 weeks ago
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆44Aug 25, 2026Updated last month
- The multi-core cluster of a PULP system.☆119Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- 1G eth UDP / IP Stack☆10Jul 17, 2014Updated 12 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- An 8b10b decoder and encoder in logic in VHDL☆28Apr 12, 2021Updated 5 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆155Mar 17, 2023Updated 3 years ago
- ☆18Sep 5, 2026Updated last month
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆285Updated this week
- Superscalar Out-of-Order NPU Design on FPGA☆18May 17, 2024Updated 2 years ago
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- uvm_starter is a simple template for starting uvm projects☆12Feb 11, 2025Updated last year
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆21Aug 25, 2026Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆95Apr 1, 2026Updated 6 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆70Sep 2, 2026Updated last month
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆45Oct 29, 2023Updated 2 years ago