pulp-platform / pulp-ethernetLinks
☆14Updated 4 months ago
Alternatives and similar repositories for pulp-ethernet
Users that are interested in pulp-ethernet are comparing it to the libraries listed below
Sorting:
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated 2 weeks ago
- RISC-V Nox core☆68Updated last month
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 8 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- SystemVerilog FSM generator☆32Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated last month
- Contains commonly used UVM components (agents, environments and tests).☆29Updated 7 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Platform Level Interrupt Controller☆41Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- ☆30Updated this week
- ☆60Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆24Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- ☆33Updated 2 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆28Updated last year
- APB UVC ported to Verilator☆11Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆76Updated 2 years ago
- ☆17Updated 3 weeks ago