pulp-platform / pulp_cluster

Related projects ⓘ

Alternatives and complementary repositories for pulp_cluster

• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 5 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆93Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆78Updated 3 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆73Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆36Updated last week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆34Updated 3 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆131Updated 3 weeks ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆56Updated last week
• ucb-bar / testchipip
  ☆80Updated last month
• chipsalliance / uvm-verilator
  ☆75Updated last year
• riscv-software-src / riscv-isac
  ☆32Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆100Updated last month
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆44Updated 2 months ago
• AlSaqr-platform / he-soc
  ☆33Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆75Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 2 weeks ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆62Updated 4 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 4 months ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆19Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆27Updated 6 months ago
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆28Updated 3 weeks ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆42Updated 3 weeks ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆46Updated this week
• pulp-platform / redmule
  ☆36Updated last week