pulp-platform / pulp_clusterLinks
The multi-core cluster of a PULP system.
☆97Updated last week
Alternatives and similar repositories for pulp_cluster
Users that are interested in pulp_cluster are comparing it to the libraries listed below
Sorting:
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 3 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆159Updated last week
- Simple runtime for Pulp platforms☆48Updated 2 weeks ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆103Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- Generic Register Interface (contains various adapters)☆120Updated 8 months ago
- ☆95Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆108Updated last week
- RISC-V Verification Interface☆92Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆207Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆77Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- ☆61Updated last week
- An energy-efficient RISC-V floating-point compute cluster.☆84Updated this week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆43Updated last month
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- A SystemVerilog source file pickler.☆57Updated 7 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆94Updated 2 months ago
- ☆135Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- ☆86Updated 2 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆214Updated last week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year