The multi-core cluster of a PULP system.
☆114May 15, 2026Updated this week
Alternatives and similar repositories for pulp_cluster
Users that are interested in pulp_cluster are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆126May 11, 2026Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆334Updated this week
- Generic Register Interface (contains various adapters)☆140Feb 24, 2026Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆212Updated this week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆89Feb 5, 2026Updated 3 months ago
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆153May 12, 2026Updated last week
- ☆104Mar 5, 2026Updated 2 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆131Updated this week
- Contains commonly used UVM components (agents, environments and tests).☆33Aug 17, 2018Updated 7 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆310Apr 1, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆269Nov 6, 2024Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆104Apr 20, 2026Updated 3 weeks ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 4 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆290Apr 30, 2026Updated 2 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆132Jul 11, 2025Updated 10 months ago
- ☆35Apr 28, 2026Updated 3 weeks ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆319Updated this week
- A Fast, Low-Overhead On-chip Network☆294May 12, 2026Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆683Apr 16, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13May 5, 2023Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆32Jan 29, 2026Updated 3 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆522May 6, 2026Updated 2 weeks ago
- tools regarding on analog modeling, validation, and generation☆23Apr 11, 2023Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆603May 7, 2026Updated last week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Mar 15, 2026Updated 2 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆552Nov 26, 2024Updated last year
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆268Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,231Apr 17, 2026Updated last month
- ☆19Apr 28, 2026Updated 3 weeks ago
- Direct Access Memory for MPSoC☆13May 3, 2026Updated 2 weeks ago
- A simple, scalable, source-synchronous, all-digital DDR link☆37Apr 7, 2026Updated last month
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 4 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆115Sep 18, 2023Updated 2 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆481May 8, 2026Updated last week