HEP-SoC / SoCMake
CMake based hardware build system
☆18Updated this week
Alternatives and similar repositories for SoCMake:
Users that are interested in SoCMake are comparing it to the libraries listed below
- An automatic clock gating utility☆47Updated 3 weeks ago
- Cross EDA Abstraction and Automation☆37Updated 2 weeks ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- ☆18Updated 10 months ago
- Library of open source Process Design Kits (PDKs)☆40Updated this week
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated this week
- ☆36Updated 2 years ago
- ☆33Updated 2 years ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- A configurable SRAM generator☆48Updated 4 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆24Updated 2 months ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- ☆12Updated 2 years ago
- Open source process design kit for 28nm open process☆55Updated last year
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- ☆31Updated 4 months ago
- LibreSilicon's Standard Cell Library Generator☆18Updated last year
- SAR ADC on tiny tapeout☆38Updated 3 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆44Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Extensible FPGA control platform☆60Updated 2 years ago
- Characterizer☆22Updated 8 months ago