HEP-SoC / SoCMakeLinks
CMake based hardware build system
☆35Updated this week
Alternatives and similar repositories for SoCMake
Users that are interested in SoCMake are comparing it to the libraries listed below
Sorting:
- SystemVerilog FSM generator☆33Updated last year
- ☆20Updated last year
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- An automatic clock gating utility☆51Updated 9 months ago
- A configurable SRAM generator☆57Updated 5 months ago
- Test dashboard for verification features in Verilator☆28Updated this week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Cross EDA Abstraction and Automation☆41Updated 2 months ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- RISC-V Nox core☆71Updated 6 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆50Updated last year
- Library of open source Process Design Kits (PDKs)☆65Updated last week
- An open source PDK using TIGFET 10nm devices.☆55Updated 3 years ago
- ☆38Updated 3 years ago
- Open source process design kit for 28nm open process☆72Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆34Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated last week
- Open Source PHY v2☆33Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 months ago
- MathLib DAC 2023 version☆13Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago