HEP-SoC / SoCMakeLinks
CMake based hardware build system
☆31Updated 3 weeks ago
Alternatives and similar repositories for SoCMake
Users that are interested in SoCMake are comparing it to the libraries listed below
Sorting:
- ☆19Updated last year
- SystemVerilog FSM generator☆32Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆51Updated this week
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- A configurable SRAM generator☆54Updated 3 weeks ago
- SystemVerilog Linter based on pyslang☆31Updated 4 months ago
- Cross EDA Abstraction and Automation☆39Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- RISC-V Nox core☆68Updated last month
- An open source PDK using TIGFET 10nm devices.☆50Updated 2 years ago
- An automatic clock gating utility☆50Updated 5 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- ☆32Updated 8 months ago
- Open Source PHY v2☆30Updated last year
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Python library for operations with VCD and other digital wave files☆52Updated 3 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 11 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Test dashboard for verification features in Verilator☆27Updated this week
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆18Updated 2 months ago
- ☆52Updated 5 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆65Updated 2 months ago