HEP-SoC / SoCMakeLinks
CMake based hardware build system
☆27Updated this week
Alternatives and similar repositories for SoCMake
Users that are interested in SoCMake are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- ☆33Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆47Updated this week
- ☆18Updated last year
- An automatic clock gating utility☆49Updated 2 months ago
- A configurable SRAM generator☆51Updated last week
- YosysHQ SVA AXI Properties☆40Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- ☆30Updated 2 months ago
- ☆36Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆32Updated 5 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- SystemVerilog Linter based on pyslang☆31Updated last month
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- RISC-V Nox core☆64Updated 3 months ago
- Cross EDA Abstraction and Automation☆39Updated 2 weeks ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated last week
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated last week
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆20Updated 6 months ago
- Open source process design kit for 28nm open process☆59Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- ☆44Updated 5 years ago
- ☆11Updated 3 weeks ago