Alternatives and similar repositories for SoCMake:

Users that are interested in SoCMake are comparing it to the libraries listed below

• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last month
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated 2 weeks ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆37Updated this week
• b224hisl / rioschip
  ☆33Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated 2 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆53Updated last year
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• efabless / caravel-lite
  ☆16Updated 4 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆27Updated 11 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• pulp-platform / svase
  ☆31Updated 2 months ago
• aolofsson / POSH
  ☆43Updated 5 years ago
• snishizawa / libretto
  Characterizer
  ☆21Updated 7 months ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆19Updated 4 months ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆30Updated 10 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆53Updated 3 weeks ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆48Updated 9 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆26Updated 10 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year