Open-source non-blocking L2 cache
☆62Jun 7, 2026Updated this week
Alternatives and similar repositories for CoupledL2
Users that are interested in CoupledL2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source high-performance non-blocking cache☆98Apr 16, 2026Updated last month
- The Unified TileLink Memory Subsystem Tester for XiangShan☆14Updated this week
- ☆17Jun 2, 2026Updated last week
- ☆14May 22, 2026Updated 3 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆107May 15, 2026Updated 3 weeks ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 6 months ago
- ☆43Jun 3, 2026Updated last week
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆229Updated this week
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆91Aug 29, 2023Updated 2 years ago
- This repo includes XiangShan's function units☆30Jun 3, 2026Updated last week
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10May 15, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆143Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆133Jul 11, 2025Updated 11 months ago
- ☆90May 29, 2026Updated last week
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 6 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆39Updated this week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆96Feb 26, 2024Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆21Jun 2, 2026Updated last week
- GPGPU supporting RISCV-V, developed with verilog HDL☆152Feb 24, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 9 months ago
- Super fast RISC-V ISA emulator for XiangShan processor☆333Jun 5, 2026Updated last week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆34May 17, 2026Updated 3 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆178Updated this week
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆236Jun 25, 2025Updated 11 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆57Aug 14, 2024Updated last year
- RISC-V Matrix Specification☆26Dec 2, 2024Updated last year
- XiangShan Frontend Develop Environment☆72May 29, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆17Mar 17, 2022Updated 4 years ago
- A hand-written recursive decent Verilog parser.☆10May 7, 2026Updated last month
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- Documentation for XiangShan☆440Updated this week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆68Jun 3, 2026Updated last week
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- Vector processor for RISC-V vector ISA☆138Oct 19, 2020Updated 5 years ago