OpenXiangShan / CoupledL2Links
Open-source non-blocking L2 cache
☆43Updated this week
Alternatives and similar repositories for CoupledL2
Users that are interested in CoupledL2 are comparing it to the libraries listed below
Sorting:
- This repo includes XiangShan's function units☆26Updated 2 weeks ago
- Open-source high-performance non-blocking cache☆83Updated 3 weeks ago
- Open source high performance IEEE-754 floating unit☆73Updated last year
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆13Updated 4 months ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year
- For contributions of Chisel IP to the chisel community.☆61Updated 7 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- An RTL generator for a last-level shared inclusive TileLink cache controller☆19Updated 5 months ago
- chipyard in mill :P☆78Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- ☆33Updated 3 months ago
- ☆30Updated 6 months ago
- ☆35Updated 3 weeks ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆95Updated 2 months ago
- Chisel RISC-V Vector 1.0 Implementation☆101Updated last month
- Unit tests generator for RVV 1.0☆88Updated last month
- ☆40Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- RISC-V Matrix Specification☆22Updated 6 months ago
- ☆64Updated last week
- A libgloss replacement for RISC-V that supports HTIF☆38Updated last year
- RISC-V IOMMU Specification☆119Updated this week
- Run Rocket Chip on VCU128☆30Updated 6 months ago
- ☆42Updated 3 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆38Updated this week
- ☆17Updated 3 years ago
- ☆46Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- AIA IP compliant with the RISC-V AIA spec☆42Updated 4 months ago