Alternatives and similar repositories for CoupledL2

Users that are interested in CoupledL2 are comparing it to the libraries listed below

• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆88Updated last week
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 4 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆109Updated last week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆27Updated this week
• sequencer / arithmetic
  ☆33Updated 5 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆102Updated last month
• chipsalliance / tilelink
  ☆34Updated 9 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆90Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆117Updated this week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆67Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 4 months ago
• pulp-platform / redmule
  ☆73Updated last week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 9 months ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆23Updated this week
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆22Updated 9 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆67Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆178Updated last week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 10 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated last year
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 7 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 4 months ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago