Open-source non-blocking L2 cache
☆55Mar 21, 2026Updated this week
Alternatives and similar repositories for CoupledL2
Users that are interested in CoupledL2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source high-performance non-blocking cache☆95Feb 13, 2026Updated last month
- The Unified TileLink Memory Subsystem Tester for XiangShan☆12Mar 6, 2026Updated 2 weeks ago
- ☆16Updated this week
- ☆12Mar 12, 2026Updated last week
- ☆97Mar 5, 2026Updated 2 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 3 months ago
- ☆42Updated this week
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆84Aug 29, 2023Updated 2 years ago
- ☆129Updated this week
- This repo includes XiangShan's function units☆30Feb 14, 2026Updated last month
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10May 15, 2021Updated 4 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆206Mar 16, 2026Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 8 months ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆91Feb 26, 2024Updated 2 years ago
- ☆88Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Feb 25, 2026Updated 3 weeks ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- Super fast RISC-V ISA emulator for XiangShan processor☆314Mar 11, 2026Updated last week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆32Mar 4, 2026Updated 2 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆172Mar 16, 2026Updated last week
- ☆224Jun 25, 2025Updated 8 months ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- RISC-V Matrix Specification☆23Dec 2, 2024Updated last year
- XiangShan Frontend Develop Environment☆69Mar 3, 2026Updated 2 weeks ago
- ☆17Mar 17, 2022Updated 4 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Mar 13, 2026Updated last week
- Documentation for XiangShan☆434Mar 16, 2026Updated last week
- GPGPU supporting RISCV-V, developed with verilog HDL☆145Feb 24, 2025Updated last year
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- Vector processor for RISC-V vector ISA☆140Oct 19, 2020Updated 5 years ago