Alternatives and similar repositories for CoupledL2

Users that are interested in CoupledL2 are comparing it to the libraries listed below

• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆93Updated 2 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆131Updated 4 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 3 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆111Updated 4 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆136Updated this week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• pulp-platform / redmule
  ☆90Updated last week
• sequencer / arithmetic
  ☆33Updated 10 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆38Updated 4 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆73Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆195Updated this week
• ucb-bar / ucie
  An open-source UCIe implementation
  ☆82Updated 2 weeks ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆29Updated this week
• chipsalliance / tilelink
  ☆38Updated last year
• OpenXiangShan / Utility
  ☆15Updated this week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆37Updated 2 months ago
• OpenXiangShan / nexus-am
  ☆42Updated last week
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆23Updated last year
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆42Updated last week
• ucb-bar / testchipip
  ☆87Updated last week
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆100Updated 2 weeks ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆107Updated last week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆163Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆77Updated last week