OpenXiangShan / CoupledL2Links
Open-source non-blocking L2 cache
☆51Updated this week
Alternatives and similar repositories for CoupledL2
Users that are interested in CoupledL2 are comparing it to the libraries listed below
Sorting:
- Open-source high-performance non-blocking cache☆92Updated 3 weeks ago
- Open source high performance IEEE-754 floating unit☆87Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆124Updated 2 months ago
- chipyard in mill :P☆77Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- ☆33Updated 9 months ago
- ☆37Updated last year
- Unit tests generator for RVV 1.0☆98Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last month
- ☆41Updated 3 weeks ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 3 months ago
- ☆89Updated last week
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- This repo includes XiangShan's function units☆28Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆130Updated last week
- A Heterogeneous GPU Platform for Chipyard SoC☆40Updated 2 weeks ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 3 months ago
- Chisel Cheatsheet☆34Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆112Updated last month
- ☆87Updated this week
- Run Rocket Chip on VCU128☆30Updated 2 months ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆22Updated 11 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- ☆82Updated last year
- Advanced Architecture Labs with CVA6☆71Updated last year
- Wrappers for open source FPU hardware implementations.☆35Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆109Updated last month