OpenXiangShan / CoupledL2
Open-source non-blocking L2 cache
☆39Updated this week
Alternatives and similar repositories for CoupledL2:
Users that are interested in CoupledL2 are comparing it to the libraries listed below
- Open-source high-performance non-blocking cache☆79Updated last week
- Open source high performance IEEE-754 floating unit☆68Updated last year
- chipyard in mill :P☆77Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆89Updated last week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 11 months ago
- ☆34Updated this week
- An RTL generator for a last-level shared inclusive TileLink cache controller☆19Updated 2 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆63Updated 7 months ago
- ☆17Updated 3 years ago
- This repo includes XiangShan's function units☆18Updated this week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆90Updated 2 weeks ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated this week
- RISC-V IOMMU Specification☆112Updated this week
- ☆32Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- RISC-V Matrix Specification☆21Updated 4 months ago
- Run Rocket Chip on VCU128☆30Updated 4 months ago
- Unit tests generator for RVV 1.0☆80Updated 2 weeks ago
- ☆64Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆143Updated 3 weeks ago
- RISC-V architecture concurrency model litmus tests☆75Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆193Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- ☆55Updated this week
- ☆38Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆103Updated last week
- Vector Acceleration IP core for RISC-V*☆175Updated this week
- Wrappers for open source FPU hardware implementations.☆31Updated last year