Alternatives and similar repositories for CoupledL2

Users that are interested in CoupledL2 are comparing it to the libraries listed below

• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆86Updated last month
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆26Updated last week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆77Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆36Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆103Updated 2 months ago
• chipsalliance / espresso
  ☆40Updated last month
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 2 months ago
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆14Updated 5 months ago
• chipsalliance / tilelink
  ☆31Updated 7 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆39Updated this week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 7 months ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆180Updated 2 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆64Updated 8 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆96Updated this week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆35Updated last month
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆20Updated 5 months ago
• sequencer / arithmetic
  ☆33Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated last week
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆101Updated last month
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆29Updated 5 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 2 months ago
• pulp-platform / redmule
  ☆68Updated this week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆168Updated last year
• ucb-bar / testchipip
  ☆84Updated last month
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆81Updated last month
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• ucb-bar / sha3
  ☆81Updated last year