pulp-platform / snitch_clusterLinks
An energy-efficient RISC-V floating-point compute cluster.
☆113Updated this week
Alternatives and similar repositories for snitch_cluster
Users that are interested in snitch_cluster are comparing it to the libraries listed below
Sorting:
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆114Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆231Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- Vector Acceleration IP core for RISC-V*☆184Updated 5 months ago
- ☆80Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated this week
- Unit tests generator for RVV 1.0☆92Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Vector processor for RISC-V vector ISA☆129Updated 5 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆108Updated 5 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆269Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆291Updated last week
- ☆59Updated last week
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆141Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- A Chisel RTL generator for network-on-chip interconnects☆215Updated 2 months ago
- ☆109Updated 2 months ago
- A high-efficiency system-on-chip for floating-point compute workloads.☆43Updated 9 months ago
- Self checking RISC-V directed tests☆113Updated 4 months ago
- Open-source RTL logic simulator with CUDA acceleration☆222Updated 3 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆188Updated this week
- ☆148Updated 2 years ago
- Generic Register Interface (contains various adapters)☆130Updated last week
- Open source high performance IEEE-754 floating unit☆85Updated last year
- RISC-V System on Chip Template☆159Updated 2 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆112Updated 3 months ago