pulp-platform / FlooNoCLinks
A Fast, Low-Overhead On-chip Network
☆221Updated 3 weeks ago
Alternatives and similar repositories for FlooNoC
Users that are interested in FlooNoC are comparing it to the libraries listed below
Sorting:
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆174Updated 9 months ago
- An AXI4 crossbar implementation in SystemVerilog☆169Updated last week
- Network on Chip Implementation written in SytemVerilog☆188Updated 2 years ago
- Verilog Configurable Cache☆181Updated 8 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆207Updated last week
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆210Updated 3 weeks ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆176Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆184Updated 2 months ago
- ☆97Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- A dynamic verification library for Chisel.☆154Updated 9 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆104Updated last year
- Various caches written in Verilog-HDL☆125Updated 10 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆131Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator