A Fast, Low-Overhead On-chip Network
☆358Oct 10, 2026Updated this week
Alternatives and similar repositories for FlooNoC
Users that are interested in FlooNoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆41Sep 28, 2026Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆246Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆200Nov 18, 2024Updated last year
- ☆27Oct 1, 2026Updated last week
- GEMM and GEMM-Ops accelerator for PULP systems☆123Sep 30, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- whatever it means☆19Jun 10, 2026Updated 4 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,716Sep 24, 2026Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆175Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆376Updated this week
- ☆254Jun 25, 2025Updated last year
- Network on Chip Implementation written in SytemVerilog☆213Aug 27, 2022Updated 4 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆152Oct 2, 2026Updated last week
- Common SystemVerilog components☆807Sep 18, 2026Updated 3 weeks ago
- ☆37Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A simple, scalable, source-synchronous, all-digital DDR link☆42Oct 1, 2026Updated last week
- A dependency management tool for hardware projects.☆395Oct 1, 2026Updated last week
- The multi-core cluster of a PULP system.☆119Updated this week
- ☆16Updated this week
- A high-efficiency system-on-chip for floating-point compute workloads.☆55Jan 13, 2025Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆329Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆689Sep 28, 2026Updated last week
- A simple superscalar out-of-order RISC-V microprocessor☆256Feb 24, 2025Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆132Sep 7, 2026Updated last month
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,095Updated this week
- Parametric AXI4 crossbar in SystemVerilog☆247May 25, 2026Updated 4 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆39May 4, 2024Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆115Sep 18, 2023Updated 3 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆259Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆552Updated this week
- A Linux-capable RISC-V multicore for and by the world☆835Updated this week
- Berkeley's Spatial Array Generator☆1,503Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A Chisel RTL generator for network-on-chip interconnects☆237Nov 7, 2025Updated 11 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆40Dec 22, 2023Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,310Oct 1, 2026Updated last week
- ☆43Apr 28, 2019Updated 7 years ago
- ☆89Oct 25, 2014Updated 11 years ago
- 32-bit Superscalar RISC-V CPU☆1,315Sep 18, 2021Updated 5 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆230Nov 22, 2023Updated 2 years ago