pulp-platform / FlooNoC
A Fast, Low-Overhead On-chip Network
☆134Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for FlooNoC
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆140Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆58Updated last week
- ☆73Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- Verilog Configurable Cache☆167Updated 2 months ago
- An AXI4 crossbar implementation in SystemVerilog☆121Updated 5 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆90Updated this week
- Network on Chip Implementation written in SytemVerilog☆156Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆57Updated 3 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆103Updated this week
- Vector processor for RISC-V vector ISA☆109Updated 4 years ago
- RISC-V Verification Interface☆74Updated 2 months ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆113Updated last month
- Opensource DDR3 Controller☆203Updated last week
- SystemVerilog synthesis tool☆168Updated this week
- Fabric generator and CAD tools☆148Updated this week
- ☆42Updated 8 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆108Updated 6 years ago
- A dynamic verification library for Chisel.☆140Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆60Updated 7 months ago
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆145Updated 2 weeks ago
- ☆160Updated 10 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆47Updated 4 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- A demo system for Ibex including debug support and some peripherals☆54Updated 2 months ago
- A Chisel RTL generator for network-on-chip interconnects☆176Updated 2 months ago
- RISC-V System on Chip Template☆153Updated this week