ucb-bar / saturn-vectors
Chisel RISC-V Vector 1.0 Implementation
☆87Updated last month
Alternatives and similar repositories for saturn-vectors:
Users that are interested in saturn-vectors are comparing it to the libraries listed below
- Unit tests generator for RVV 1.0☆79Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆99Updated last week
- Tests for example Rocket Custom Coprocessors☆72Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆66Updated last week
- Vector Acceleration IP core for RISC-V*☆172Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- high-performance RTL simulator☆153Updated 9 months ago
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆67Updated last year
- Vector processor for RISC-V vector ISA☆115Updated 4 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆87Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆69Updated last week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 11 months ago
- RiVEC Bencmark Suite☆113Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆181Updated 2 weeks ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆96Updated last year
- Advanced Architecture Labs with CVA6☆54Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- ☆33Updated 8 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated 11 months ago
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆34Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆96Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated 11 months ago
- ☆37Updated last week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆55Updated last month