ucb-bar / saturn-vectorsLinks
Chisel RISC-V Vector 1.0 Implementation
☆103Updated 2 months ago
Alternatives and similar repositories for saturn-vectors
Users that are interested in saturn-vectors are comparing it to the libraries listed below
Sorting:
- Unit tests generator for RVV 1.0☆88Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- Vector Acceleration IP core for RISC-V*☆180Updated 2 months ago
- Open source high performance IEEE-754 floating unit☆77Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- high-performance RTL simulator☆168Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆106Updated 2 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆91Updated this week
- ☆105Updated last month
- ☆47Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆169Updated 3 weeks ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- The multi-core cluster of a PULP system.☆104Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- ☆68Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆112Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 2 months ago
- RiVEC Bencmark Suite☆117Updated 7 months ago
- (System)Verilog to Chisel translator☆115Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆101Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆109Updated last month
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆170Updated 6 months ago
- Open-source high-performance non-blocking cache☆86Updated last month
- Open-source RTL logic simulator with CUDA acceleration☆187Updated 3 weeks ago
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆35Updated last month