ucb-bar / saturn-vectorsLinks
Chisel RISC-V Vector 1.0 Implementation
☆101Updated last month
Alternatives and similar repositories for saturn-vectors
Users that are interested in saturn-vectors are comparing it to the libraries listed below
Sorting:
- Unit tests generator for RVV 1.0☆88Updated last month
- ☆46Updated last week
- Vector Acceleration IP core for RISC-V*☆179Updated last month
- high-performance RTL simulator☆159Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- Open source high performance IEEE-754 floating unit☆73Updated last year
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- RISC-V Matrix Specification☆22Updated 6 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 7 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆95Updated last month
- ☆64Updated last week
- RiVEC Bencmark Suite☆117Updated 6 months ago
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆111Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆82Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- The multi-core cluster of a PULP system.☆101Updated this week
- Self checking RISC-V directed tests☆108Updated 2 weeks ago
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- The specification for the FIRRTL language☆57Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆202Updated last month
- Pure digital components of a UCIe controller☆63Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆88Updated last week
- ☆35Updated 11 months ago
- Advanced Architecture Labs with CVA6☆62Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated last week