Chisel RISC-V Vector 1.0 Implementation
☆158Oct 15, 2026Updated this week
Alternatives and similar repositories for saturn-vectors
Users that are interested in saturn-vectors are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Rocket-based RISC-V superscalar in-order core☆42Aug 31, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆552Updated this week
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Oct 10, 2026Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆176Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆264Oct 9, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆15Sep 30, 2026Updated 2 weeks ago
- ☆324Jul 22, 2026Updated 2 months ago
- Unit tests generator for RVV 1.0☆118May 25, 2026Updated 4 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆154Aug 14, 2026Updated 2 months ago
- ☆18Mar 11, 2026Updated 7 months ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆62Jan 20, 2026Updated 8 months ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆69Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,424Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Berkeley's Spatial Array Generator☆1,516Updated this week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆262Oct 9, 2026Updated last week
- RISC-V Integrated Matrix Development Repository☆27Updated this week
- Open-source non-blocking L2 cache☆65Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆187Apr 1, 2026Updated 6 months ago
- ☆14Aug 31, 2025Updated last year
- A fork of Xiangshan for AI☆62Updated this week
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆39Oct 23, 2025Updated 11 months ago
- GEMM and GEMM-Ops accelerator for PULP systems☆126Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 10 years ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆16Aug 30, 2023Updated 3 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆21Oct 5, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,261Oct 8, 2026Updated last week
- A Fast, Low-Overhead On-chip Network☆362Oct 10, 2026Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆239Nov 7, 2025Updated 11 months ago
- Administrative repository for the Attached Matrix Facility Task Group☆15Dec 11, 2023Updated 2 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆107Sep 12, 2026Updated last month
- Vector processor for RISC-V vector ISA☆147Oct 19, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Jul 16, 2026Updated 3 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆61Oct 8, 2026Updated last week
- ☆328Jan 23, 2026Updated 8 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆40Oct 8, 2026Updated last week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- ☆2,323Updated this week
- ☆92Updated this week