yonseicasl / NPUsimLinks
NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
☆36Updated 6 months ago
Alternatives and similar repositories for NPUsim
Users that are interested in NPUsim are comparing it to the libraries listed below
Sorting:
- ☆31Updated 3 months ago
- ☆15Updated last week
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 3 weeks ago
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A Toy-Purpose TPU Simulator☆19Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆35Updated last month
- ☆36Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 8 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- ☆30Updated 8 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆58Updated 7 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- The official NaplesPU hardware code repository☆17Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆21Updated 9 years ago
- STONNE Simulator integrated into SST Simulator☆20Updated last year
- ☆47Updated 2 months ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆15Updated 2 weeks ago
- ☆60Updated 2 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆19Updated 6 months ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆21Updated last year
- ☆92Updated last year
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆29Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago