RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and generative AI with configurable precision (FP32/16/BF16/INT8).
☆26Apr 25, 2025Updated last year
Alternatives and similar repositories for TensorGPGPU
Users that are interested in TensorGPGPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 7 months ago
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated 2 years ago
- ☆21Jan 13, 2026Updated 10 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆29Nov 2, 2026Updated last week
- Personal Project, Implementation of tinyNPU☆13Oct 14, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of…☆20Mar 30, 2025Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆65Jan 20, 2026Updated 9 months ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- A simple first-order simulator for softmax☆11Sep 22, 2025Updated last year
- Software generation for Bare-metal RISC-V + NVDLA SoC☆13Sep 5, 2025Updated last year
- Reimplementation of paper EIE by Stanford Song Han☆10Mar 18, 2021Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆57Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- RTL implementation of a ray-tracing GPU☆18Dec 18, 2012Updated 13 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆37Jul 17, 2025Updated last year
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆18Jun 24, 2026Updated 4 months ago
- This is a brand new implement of GPGPU called Koala GPU which will be compatible with NV GPU micro architecture starting from fermi. It s…☆20May 31, 2026Updated 5 months ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆19Sep 21, 2025Updated last year
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 3 years ago
- ☆14Nov 4, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- Izumi is an instruction pipeline visualizer for Onikiri2-Kanata format based on Konata.☆14Nov 5, 2026Updated last week
- N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28n…☆24Jun 14, 2026Updated 4 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆58Nov 3, 2026Updated last week
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Oct 30, 2026Updated 2 weeks ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- ☆24Sep 26, 2025Updated last year
- ☆26Apr 18, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆46Oct 21, 2025Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆210Apr 15, 2026Updated 6 months ago
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- Learn and build GPU RTL from scratch☆23Aug 1, 2025Updated last year
- ☆11Sep 21, 2026Updated last month
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆20Aug 14, 2026Updated 2 months ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆18Aug 11, 2026Updated 3 months ago
Are these results useful?