RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and generative AI with configurable precision (FP32/16/BF16/INT8).
☆21Apr 25, 2025Updated 10 months ago
Alternatives and similar repositories for TensorGPGPU
Users that are interested in TensorGPGPU are comparing it to the libraries listed below
Sorting:
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 2 weeks ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆28Apr 24, 2025Updated 10 months ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆49Jan 20, 2026Updated last month
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- ☆21Feb 20, 2026Updated 2 weeks ago
- ☆13Jan 16, 2026Updated last month
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago
- Open-source Neural Processing Unit (NPU) from China ❤☆37Jan 29, 2025Updated last year
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- A Heterogeneous GPU Platform for Chipyard SoC☆44Updated this week
- ☆13Jul 28, 2022Updated 3 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- ☆13May 8, 2025Updated 10 months ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- A Toy-Purpose TPU Simulator☆22Jun 7, 2024Updated last year
- ☆17Dec 21, 2020Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- ☆18May 13, 2025Updated 9 months ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Mar 3, 2026Updated last week
- ☆10Dec 15, 2023Updated 2 years ago
- ☆32Jan 21, 2026Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆85Nov 26, 2025Updated 3 months ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- ET Accelerator Firmware and Runtime☆35Updated this week
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Feb 28, 2026Updated last week
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- RV64GC Linux Capable RISC-V Core☆54Oct 20, 2025Updated 4 months ago
- 【2024年新版】国科大 陈云霁 智能计算系统AICS实验代码☆13May 31, 2024Updated last year
- An open-source UCIe implementation developed at UC Berkeley.☆20Jul 8, 2024Updated last year