Generic Register Interface (contains various adapters)
☆140May 15, 2026Updated 3 weeks ago
Alternatives and similar repositories for register_interface
Users that are interested in register_interface are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Common SystemVerilog components☆755Updated this week
- The multi-core cluster of a PULP system.☆114May 27, 2026Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆212Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆270Nov 6, 2024Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆89Feb 5, 2026Updated 4 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆311Apr 1, 2026Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- ☆107May 15, 2026Updated 3 weeks ago
- ☆16May 6, 2026Updated last month
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆126Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,591Jun 1, 2026Updated last week
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated 4 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆609May 26, 2026Updated 2 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- AXI Adapter(s) for RISC-V Atomic Operations☆66Jun 2, 2026Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆684May 27, 2026Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆292Apr 30, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆132Jul 11, 2025Updated 10 months ago
- Simple single-port AXI memory interface☆50Jun 7, 2024Updated 2 years ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆319May 20, 2026Updated 2 weeks ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆226Jan 11, 2026Updated 4 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆338Jun 1, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,243May 29, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- BaseJump STL: A Standard Template Library for SystemVerilog☆668May 11, 2026Updated 3 weeks ago
- CORE-V Family of RISC-V Cores☆353Mar 31, 2026Updated 2 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆341Dec 11, 2024Updated last year
- ☆13May 5, 2023Updated 3 years ago
- A simple, basic, formally verified UART controller☆339Jan 29, 2024Updated 2 years ago
- Verilog Configurable Cache☆199May 25, 2026Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆106May 22, 2026Updated 2 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆38May 4, 2024Updated 2 years ago
- Verilog AXI stream components for FPGA implementation☆893Feb 27, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V CPU Core☆433Jun 24, 2025Updated 11 months ago
- Verilog digital signal processing components☆184Oct 30, 2022Updated 3 years ago
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated 3 months ago
- ☆19Apr 28, 2026Updated last month
- Opensource DDR3 Controller☆446May 21, 2026Updated 2 weeks ago
- AMBA AXI VIP☆464Jun 28, 2024Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆600Oct 10, 2021Updated 4 years ago