Tile based architecture designed for computing efficiency, scalability and generality
☆289Mar 30, 2026Updated 3 weeks ago
Alternatives and similar repositories for bsg_manycore
Users that are interested in bsg_manycore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Mar 15, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆661Apr 7, 2026Updated last week
- A Linux-capable RISC-V multicore for and by the world☆794Apr 8, 2026Updated last week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆318Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Jun 16, 2025Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆591Apr 7, 2026Updated last week
- The OpenPiton Platform☆782Feb 25, 2026Updated last month
- The multi-core cluster of a PULP system.☆113Mar 28, 2026Updated 3 weeks ago
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated last month
- Common SystemVerilog components☆736Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,546Apr 11, 2026Updated last week
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- Verilog Configurable Cache☆195Mar 9, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆267Nov 6, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,217Updated this week
- VeeR EH1 core☆934May 29, 2023Updated 2 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆315Mar 6, 2026Updated last month
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,166Feb 21, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆505Apr 10, 2026Updated last week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆408Updated this week
- 32-bit Superscalar RISC-V CPU☆1,235Sep 18, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Fast, Low-Overhead On-chip Network☆280Updated this week
- ☆102Mar 5, 2026Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆978Nov 15, 2024Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆204Apr 8, 2026Updated last week
- An open-source static random access memory (SRAM) compiler.☆1,039Apr 8, 2026Updated last week
- ☆1,970Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆130Jul 11, 2025Updated 9 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,008Mar 9, 2026Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆145Updated this week
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆457Apr 5, 2026Updated 2 weeks ago
- VRoom! RISC-V CPU☆519Sep 2, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,219Apr 1, 2026Updated 2 weeks ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆449Apr 5, 2026Updated 2 weeks ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆379Oct 19, 2023Updated 2 years ago
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated 2 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,125Mar 11, 2026Updated last month