bespoke-silicon-group / bsg_manycore
Tile based architecture designed for computing efficiency, scalability and generality
☆249Updated 2 weeks ago
Alternatives and similar repositories for bsg_manycore:
Users that are interested in bsg_manycore are comparing it to the libraries listed below
- RISC-V RV64GC emulator designed for RTL co-simulation☆223Updated 4 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- Instruction Set Generator initially contributed by Futurewei☆274Updated last year
- Verilog Configurable Cache☆174Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆182Updated this week
- ☆310Updated 6 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- VeeR EL2 Core☆268Updated this week
- ☆279Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆170Updated 7 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆158Updated 2 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 4 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆220Updated last year
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 6 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆268Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆189Updated 2 weeks ago
- ☆231Updated 2 years ago
- RISC-V Torture Test☆186Updated 8 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆206Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆169Updated this week
- ☆131Updated last year
- ☆169Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆234Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆139Updated 2 weeks ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆150Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆150Updated last year
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆288Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆560Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆362Updated 2 weeks ago