Tile based architecture designed for computing efficiency, scalability and generality
☆285Feb 20, 2026Updated last month
Alternatives and similar repositories for bsg_manycore
Users that are interested in bsg_manycore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Mar 15, 2026Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆654Jan 19, 2026Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆787Updated this week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆315Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Jun 16, 2025Updated 9 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆580Mar 11, 2026Updated 2 weeks ago
- The OpenPiton Platform☆779Feb 25, 2026Updated last month
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated 2 weeks ago
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated last month
- Common SystemVerilog components☆728Mar 23, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,528Mar 18, 2026Updated last week
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- Verilog Configurable Cache☆193Mar 9, 2026Updated 3 weeks ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆264Nov 6, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,203May 26, 2025Updated 10 months ago
- VeeR EH1 core☆931May 29, 2023Updated 2 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆315Mar 6, 2026Updated 3 weeks ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,159Feb 21, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆500Mar 18, 2026Updated last week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆407Updated this week
- 32-bit Superscalar RISC-V CPU☆1,207Sep 18, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A Fast, Low-Overhead On-chip Network☆272Updated this week
- ☆97Mar 5, 2026Updated 3 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆201Mar 6, 2026Updated 3 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆973Nov 15, 2024Updated last year
- An open-source static random access memory (SRAM) compiler.☆1,024Mar 12, 2026Updated 2 weeks ago
- ☆1,947Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 8 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,006Mar 9, 2026Updated 3 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆140Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆454Mar 8, 2026Updated 3 weeks ago
- VRoom! RISC-V CPU☆518Sep 2, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,194Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆446Mar 6, 2026Updated 3 weeks ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆377Oct 19, 2023Updated 2 years ago
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,116Mar 11, 2026Updated 2 weeks ago