Tile based architecture designed for computing efficiency, scalability and generality
☆291Apr 30, 2026Updated last month
Alternatives and similar repositories for bsg_manycore
Users that are interested in bsg_manycore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Mar 15, 2026Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆668May 11, 2026Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆805Apr 24, 2026Updated last month
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆319May 20, 2026Updated last week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆45Jun 16, 2025Updated 11 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆606Updated this week
- The OpenPiton Platform☆792Feb 25, 2026Updated 3 months ago
- The multi-core cluster of a PULP system.☆114May 25, 2026Updated last week
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated 2 weeks ago
- Common SystemVerilog components☆754Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,584May 19, 2026Updated last week
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- Verilog Configurable Cache☆198May 21, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V RV64GC emulator designed for RTL co-simulation☆241Nov 20, 2024Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆270Nov 6, 2024Updated last year
- VeeR EH1 core☆945May 29, 2023Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,235Apr 17, 2026Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆321Mar 6, 2026Updated 2 months ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,179Feb 21, 2026Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,250Sep 18, 2021Updated 4 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆523May 6, 2026Updated 3 weeks ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆412Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Fast, Low-Overhead On-chip Network☆301May 12, 2026Updated 2 weeks ago
- VRoom! RISC-V CPU☆520Sep 2, 2024Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆981Nov 15, 2024Updated last year
- ☆2,038Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆212May 21, 2026Updated last week
- ☆106May 15, 2026Updated 2 weeks ago
- An open-source static random access memory (SRAM) compiler.☆1,065May 15, 2026Updated 2 weeks ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,015May 19, 2026Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆156Updated this week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆132Jul 11, 2025Updated 10 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆453Apr 5, 2026Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,270May 19, 2026Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆682Apr 16, 2026Updated last month
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆381Oct 19, 2023Updated 2 years ago
- SERV - The SErial RISC-V CPU☆1,806Feb 19, 2026Updated 3 months ago