bespoke-silicon-group / bsg_manycore
Tile based architecture designed for computing efficiency, scalability and generality
☆230Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for bsg_manycore
- RISC-V RV64GC emulator designed for RTL co-simulation☆217Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆438Updated 3 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆266Updated last year
- RISC-V Torture Test☆167Updated 4 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆215Updated 2 weeks ago
- ☆291Updated 2 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆150Updated 2 months ago
- Verilog Configurable Cache☆167Updated 2 months ago
- VeeR EL2 Core☆251Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 3 months ago
- ☆215Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆218Updated 11 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆146Updated last week
- ☆269Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆255Updated last week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆127Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆177Updated 2 months ago
- ☆161Updated 11 months ago
- ☆122Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆225Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆526Updated this week
- A dynamic verification library for Chisel.☆142Updated last week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆343Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆291Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆379Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆148Updated 9 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆153Updated 4 years ago
- Common SystemVerilog components☆518Updated this week
- RISC-V CPU Core☆288Updated 5 months ago