pulp-platform / neurekaLinks
2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
☆28Updated last week
Alternatives and similar repositories for neureka
Users that are interested in neureka are comparing it to the libraries listed below
Sorting:
- ☆90Updated this week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- matrix-coprocessor for RISC-V☆30Updated last month
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- ☆29Updated 6 years ago
- The official NaplesPU hardware code repository☆22Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- ☆33Updated 2 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated this week
- The multi-core cluster of a PULP system.☆111Updated last week
- PCI Express controller model☆71Updated 3 years ago
- Simple runtime for Pulp platforms☆50Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Updated 10 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- RISC-V Matrix Specification☆23Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Updated 3 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- ☆74Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated this week
- A simple, scalable, source-synchronous, all-digital DDR link☆36Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- BlackParrot on Zynq☆48Updated this week
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago