pulp-platform / neureka
2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
☆24Updated this week
Alternatives and similar repositories for neureka
Users that are interested in neureka are comparing it to the libraries listed below
Sorting:
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆34Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- ☆27Updated last month
- ☆61Updated 2 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆56Updated 3 months ago
- ☆59Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated this week
- Reconfigurable Binary Engine☆16Updated 4 years ago
- The multi-core cluster of a PULP system.☆92Updated this week
- Pulp virtual platform☆23Updated 2 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 11 months ago
- Simple runtime for Pulp platforms☆47Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆17Updated 6 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆54Updated 4 months ago
- matrix-coprocessor for RISC-V☆14Updated 3 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- BlackParrot on Zynq☆41Updated 2 months ago
- Chisel Things for OFDM☆31Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago