ic-lab-duth / DRIM-SLinks
DUTH RISC-V Superscalar Microprocessor
☆32Updated last year
Alternatives and similar repositories for DRIM-S
Users that are interested in DRIM-S are comparing it to the libraries listed below
Sorting:
- ☆32Updated last week
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- DUTH RISC-V Microprocessor☆22Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- ☆31Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆20Updated last month
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆29Updated this week
- ☆13Updated 6 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆32Updated this week
- Chisel implementation of Neural Processing Unit for System on the Chip☆23Updated 3 months ago
- A Verilog implementation of a processor cache.☆32Updated 7 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 8 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 6 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- matrix-coprocessor for RISC-V☆25Updated 7 months ago
- Platform Level Interrupt Controller☆44Updated last year
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆26Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago