pulp-platform / common_cellsLinks
Common SystemVerilog components
☆672Updated 2 weeks ago
Alternatives and similar repositories for common_cells
Users that are interested in common_cells are comparing it to the libraries listed below
Sorting:
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆539Updated 3 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆613Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆609Updated 3 weeks ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆446Updated 5 months ago
- SystemVerilog to Verilog conversion☆671Updated last week
- Bus bridges and other odds and ends☆602Updated 6 months ago
- lowRISC Style Guides☆462Updated 4 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,397Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆744Updated this week
- RISC-V CPU Core☆392Updated 4 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆519Updated 11 months ago
- The UVM written in Python☆479Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- Instruction Set Generator initially contributed by Futurewei☆298Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆386Updated last month
- A DDR3 memory controller in Verilog for various FPGAs☆528Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,121Updated 4 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆459Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,136Updated 5 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆469Updated 3 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆347Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆278Updated 3 weeks ago
- VeeR EL2 Core☆302Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆425Updated 2 months ago
- synthesiseable ieee 754 floating point library in verilog☆684Updated 2 years ago
- VeeR EH1 core☆904Updated 2 years ago
- AMBA AXI VIP☆426Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆939Updated 11 months ago
- Verilog AXI stream components for FPGA implementation☆838Updated 8 months ago
- ☆354Updated 2 months ago