Alternatives and similar repositories for common_cells:

Users that are interested in common_cells are comparing it to the libraries listed below

• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆455Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆491Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆550Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆590Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,203Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆520Updated 2 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆399Updated 2 weeks ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆306Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆658Updated last week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆473Updated 2 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆408Updated 3 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆272Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆263Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆388Updated 5 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆243Updated 3 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆401Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,010Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆308Updated 8 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆846Updated last year
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆398Updated this week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆264Updated 4 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆170Updated 2 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆378Updated 7 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆776Updated 6 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆300Updated 9 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆381Updated 2 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆592Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆233Updated last year
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆898Updated 3 months ago