pulp-platform / common_cellsLinks
Common SystemVerilog components
☆704Updated last month
Alternatives and similar repositories for common_cells
Users that are interested in common_cells are comparing it to the libraries listed below
Sorting:
- BaseJump STL: A Standard Template Library for SystemVerilog☆641Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆568Updated 3 months ago
- Bus bridges and other odds and ends☆632Updated 9 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆457Updated 8 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,487Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆653Updated this week
- SystemVerilog to Verilog conversion☆699Updated 2 months ago
- lowRISC Style Guides☆476Updated 3 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆539Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆558Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆414Updated 4 months ago
- The UVM written in Python☆499Updated last week
- A Linux-capable RISC-V multicore for and by the world☆759Updated this week
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆601Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆485Updated 2 months ago
- RISC-V CPU Core☆405Updated 7 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆292Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆334Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,176Updated 8 months ago
- synthesiseable ieee 754 floating point library in verilog☆717Updated 2 years ago
- VeeR EL2 Core☆316Updated last month
- AMBA AXI VIP☆446Updated last year
- Verilog AXI stream components for FPGA implementation☆858Updated 11 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆357Updated this week
- 32-bit Superscalar RISC-V CPU☆1,176Updated 4 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆442Updated 5 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆960Updated last year
- Instruction Set Generator initially contributed by Futurewei☆305Updated 2 years ago
- AXI interface modules for Cocotb☆310Updated 4 months ago
- training labs and examples☆447Updated 3 years ago