pulp-platform / common_cellsLinks
Common SystemVerilog components
☆649Updated this week
Alternatives and similar repositories for common_cells
Users that are interested in common_cells are comparing it to the libraries listed below
Sorting:
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆525Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆598Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆583Updated this week
- SystemVerilog to Verilog conversion☆659Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,353Updated last week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆438Updated 3 months ago
- lowRISC Style Guides☆448Updated 2 months ago
- Bus bridges and other odds and ends☆582Updated 4 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆509Updated 8 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆502Updated 3 years ago
- The UVM written in Python☆449Updated last month
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆363Updated last year
- A Linux-capable RISC-V multicore for and by the world☆721Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆453Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,109Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆338Updated this week
- VeeR EL2 Core☆294Updated last week
- AMBA AXI VIP☆416Updated last year
- Verilog AXI stream components for FPGA implementation☆819Updated 5 months ago
- Instruction Set Generator initially contributed by Futurewei☆292Updated last year
- RISC-V CPU Core☆369Updated last month
- VeeR EH1 core☆889Updated 2 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆273Updated 5 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆323Updated 8 months ago
- synthesiseable ieee 754 floating point library in verilog☆664Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,086Updated 3 years ago
- Code generation tool for control and status registers☆418Updated this week
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆345Updated 2 weeks ago
- AXI interface modules for Cocotb☆276Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆266Updated 4 months ago