Alternatives and similar repositories for LOROF

Users that are interested in LOROF are comparing it to the libraries listed below

• yhinai / TensorGPGPU
  RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…
  ☆19Updated 8 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆33Updated last year
• Purdue-SoCET / atalla
  Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
  ☆21Updated 3 weeks ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆21Updated 6 years ago
• wjoeyzhewei / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆11Updated 6 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆31Updated this week
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆20Updated 9 months ago
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆40Updated last week
• robgiorgi / freess
  RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm
  ☆27Updated 2 months ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆16Updated 6 years ago
• pulp-platform / ace
  ☆20Updated 2 weeks ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆18Updated 10 months ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆21Updated 9 months ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• pulp-platform / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆18Updated last month
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆31Updated 2 weeks ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆33Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• nullromo / compression-accelerator
  Implementation of the Snappy compression algorithm as a RoCC accelerator
  ☆12Updated 6 years ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆20Updated 3 years ago
• bsc-loca / mmu
  ☆15Updated 7 months ago
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last month
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆48Updated 3 weeks ago
• pulp-platform / axi_llc
  ☆33Updated last month
• Aquaticfuller / OpenExSys_NoC
  OpenExSys_NoC a mesh-based network on chip IP.
  ☆19Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated 3 months ago
• kyaso / py-v
  A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.
  ☆17Updated 4 months ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆26Updated 3 weeks ago
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 3 years ago