Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU
☆19Oct 24, 2026Updated last week
Alternatives and similar repositories for LOROF
Users that are interested in LOROF are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Dual-Core Out-of-Order MIPS CPU Design☆26May 8, 2025Updated last year
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆39Updated this week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Feb 17, 2022Updated 4 years ago
- ☆23Sep 18, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of…☆20Mar 30, 2025Updated last year
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated 2 years ago
- ☆18Aug 17, 2026Updated 2 months ago
- ☆17Aug 26, 2025Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆13Oct 9, 2026Updated 3 weeks ago
- Repository to hold fabscalar project and simulations☆13Mar 17, 2015Updated 11 years ago
- Software generation for Bare-metal RISC-V + NVDLA SoC☆13Sep 5, 2025Updated last year
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆29Updated this week
- UM-SJTU JI VE450 2021 Summer Capstone Design Project☆10Aug 4, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆14Jun 9, 2026Updated 4 months ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Apr 6, 2023Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- ☆328Jan 23, 2026Updated 9 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated 2 years ago
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- GEMM and GEMM-Ops accelerator for PULP systems☆126Oct 22, 2026Updated last week
- ☆19Aug 27, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆38Oct 5, 2026Updated 3 weeks ago
- ☆105Oct 15, 2026Updated 2 weeks ago
- ☆13Mar 25, 2022Updated 4 years ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆36Jul 1, 2026Updated 3 months ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆14Jan 5, 2018Updated 8 years ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆71Updated this week
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆16Nov 23, 2018Updated 7 years ago
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆25Apr 25, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆42Sep 30, 2026Updated last month
- ☆33Apr 10, 2026Updated 6 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆39May 4, 2024Updated 2 years ago
- ☆21Jan 13, 2026Updated 9 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- Loongarch Emulator☆20Mar 14, 2025Updated last year