☆35Jun 4, 2026Updated last week
Alternatives and similar repositories for axi_llc
Users that are interested in axi_llc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple, scalable, source-synchronous, all-digital DDR link☆38Apr 7, 2026Updated 2 months ago
- ☆23May 25, 2026Updated 2 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆38May 4, 2024Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆215Updated this week
- A reliable, real-time subsystem for the Carfield SoC☆20Dec 2, 2025Updated 6 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A Fast, Low-Overhead On-chip Network☆304Updated this week
- ☆19Apr 28, 2026Updated last month
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆338Jun 1, 2026Updated last week
- ☆37May 22, 2026Updated 2 weeks ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆32Nov 3, 2025Updated 7 months ago
- The multi-core cluster of a PULP system.☆114Updated this week
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆27Jan 6, 2026Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆106May 22, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Intel Compiler for SystemC☆30Jun 1, 2023Updated 3 years ago
- ☆107May 15, 2026Updated 3 weeks ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆49May 10, 2024Updated 2 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- CV32E40X Design-Verification environment☆16Jun 2, 2026Updated last week
- ☆13May 5, 2023Updated 3 years ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆19Feb 27, 2025Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆89Feb 5, 2026Updated 4 months ago
- The official NaplesPU hardware code repository☆30Jul 27, 2019Updated 6 years ago
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Mar 23, 2025Updated last year
- Simple UVM testbench development using the uvmtb_template files☆25Jan 16, 2025Updated last year
- ☆28Aug 28, 2024Updated last year
- Public release☆59Sep 3, 2019Updated 6 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Sep 18, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆27Apr 24, 2019Updated 7 years ago
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 7 months ago
- ☆29Oct 20, 2019Updated 6 years ago
- A SystemVerilog source file pickler.☆61Oct 20, 2024Updated last year
- ☆24Oct 8, 2019Updated 6 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆54Mar 30, 2026Updated 2 months ago