Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
☆102Aug 20, 2026Updated 2 months ago
Alternatives and similar repositories for tech_cells_generic
Users that are interested in tech_cells_generic are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Common SystemVerilog components☆810Sep 18, 2026Updated last month
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated 2 months ago
- The multi-core cluster of a PULP system.☆122Oct 5, 2026Updated 3 weeks ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆132Sep 7, 2026Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆332Sep 15, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆250Updated this week
- GEMM and GEMM-Ops accelerator for PULP systems☆126Oct 22, 2026Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆179Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆384Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆733Oct 19, 2026Updated last week
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆17Oct 14, 2026Updated 2 weeks ago
- Verilog digital signal processing components☆197Oct 30, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- SystemVerilog modules and classes commonly used for verification☆58Jan 5, 2026Updated 9 months ago
- A modular hardware abstraction library☆53Updated this week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆331Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆287Nov 6, 2024Updated last year
- pulp_soc is the core building component of PULP based SoCs☆86Jul 17, 2026Updated 3 months ago
- Simple runtime for Pulp platforms☆56Jul 7, 2026Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆647Sep 14, 2026Updated last month
- RISC-V CPU Core☆454Jun 24, 2025Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆321Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆294Updated this week
- ☆28Apr 17, 2026Updated 6 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week
- Netlist API (and more) for EDA flow development☆165Updated this week
- ☆39Oct 22, 2026Updated last week
- IHP SG13CMOS5L PDK☆19Sep 23, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,738Sep 24, 2026Updated last month
- ☆68Mar 31, 2025Updated last year
- A dependency management tool for hardware projects.☆401Oct 22, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆16Oct 5, 2026Updated 3 weeks ago
- ☆42Oct 16, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,317Oct 20, 2026Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆303Sep 20, 2026Updated last month
- [UNRELEASED] FP div/sqrt unit for transprecision☆28Jul 27, 2026Updated 3 months ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆39Sep 21, 2026Updated last month
- A DDR3 memory controller in Verilog for various FPGAs☆642Oct 10, 2021Updated 5 years ago