Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
☆83Feb 5, 2026Updated 3 weeks ago
Alternatives and similar repositories for tech_cells_generic
Users that are interested in tech_cells_generic are comparing it to the libraries listed below
Sorting:
- Common SystemVerilog components☆713Updated this week
- The multi-core cluster of a PULP system.☆111Feb 2, 2026Updated 3 weeks ago
- Generic Register Interface (contains various adapters)☆136Feb 14, 2026Updated 2 weeks ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆119Updated this week
- ☆93Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆295Feb 4, 2026Updated 3 weeks ago
- Functional verification project for the CORE-V family of RISC-V cores.☆661Updated this week
- Simple runtime for Pulp platforms☆51Feb 2, 2026Updated 3 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆196Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- pulp_soc is the core building component of PULP based SoCs☆82Mar 10, 2025Updated 11 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆138Updated this week
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated last month
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆313Feb 11, 2026Updated 2 weeks ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 3 years ago
- ☆20Updated this week
- Verilog digital signal processing components☆171Oct 30, 2022Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆570Oct 21, 2025Updated 4 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆26Sep 9, 2025Updated 5 months ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated this week
- Verilog hardware abstraction library☆46Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,500Updated this week
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆20Jan 6, 2026Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆258Nov 6, 2024Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆155Oct 31, 2024Updated last year
- HW Design Collateral for Caliptra RoT IP☆128Feb 20, 2026Updated last week
- ☆34Feb 17, 2026Updated last week
- A Fast, Low-Overhead On-chip Network☆269Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,187May 26, 2025Updated 9 months ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆35Mar 25, 2020Updated 5 years ago
- Simple single-port AXI memory interface☆49Jun 7, 2024Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated last month
- A Python package for testing hardware (part of the magma ecosystem)☆47Mar 11, 2024Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆279Feb 20, 2026Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆318Feb 20, 2026Updated last week