Alternatives and similar repositories for tech_cells_generic

Users that are interested in tech_cells_generic are comparing it to the libraries listed below

• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆105Updated last week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated last week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆123Updated last month
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆171Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 4 months ago
• pulp-platform / redmule
  ☆71Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆113Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆99Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last month
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆88Updated last week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆138Updated 2 weeks ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆68Updated 7 months ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆126Updated last week
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆44Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆64Updated 8 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆110Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆122Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆66Updated last week
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆89Updated 4 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 9 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year