Alternatives and similar repositories for tech_cells_generic

Users that are interested in tech_cells_generic are comparing it to the libraries listed below

• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆97Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 2 weeks ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆120Updated 8 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆77Updated this week
• chipsalliance / uvm-verilator
  ☆95Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated last year
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆47Updated 7 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆92Updated this week
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆48Updated 4 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆160Updated this week
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆41Updated 11 months ago
• riscv-software-src / riscv-isac
  ☆32Updated 7 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 5 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆89Updated this week
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆43Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆135Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 8 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆31Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 6 months ago
• pulp-platform / redmule
  ☆61Updated last week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• The-OpenROAD-Project / megaboom
  ☆25Updated this week