pulp-platform / tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
☆36Updated last month
Related projects ⓘ
Alternatives and complementary repositories for tech_cells_generic
- The multi-core cluster of a PULP system.☆56Updated last week
- Simple single-port AXI memory interface☆37Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- Generic Register Interface (contains various adapters)☆100Updated last month
- Simple runtime for Pulp platforms☆36Updated last week
- AXI X-Bar☆19Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 6 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆60Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- ☆33Updated this week
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆56Updated 2 weeks ago
- Verilog behavioral description of various memories☆30Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- ☆37Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- ☆57Updated 3 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- SystemVerilog modules and classes commonly used for verification☆44Updated this week
- ☆32Updated 2 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 6 months ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 8 months ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated last month
- ☆75Updated 2 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago