AlSaqr-platform / he-socLinks
☆31Updated this week
Alternatives and similar repositories for he-soc
Users that are interested in he-soc are comparing it to the libraries listed below
Sorting:
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- Simple runtime for Pulp platforms☆48Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- ☆29Updated last month
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- Platform Level Interrupt Controller☆40Updated last year
- The multi-core cluster of a PULP system.☆97Updated last week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆43Updated last month
- RISC-V Nexus Trace TG documentation and reference code☆51Updated 5 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 2 weeks ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- RISC-V Nox core☆62Updated 2 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- ☆24Updated 2 weeks ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated last year
- ☆59Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 5 months ago