AlSaqr-platform / he-soc
☆32Updated this week
Alternatives and similar repositories for he-soc:
Users that are interested in he-soc are comparing it to the libraries listed below
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆42Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆69Updated this week
- RISCV core RV32I/E.4 threads in a ring architecture☆31Updated last year
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆58Updated 3 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- DUTH RISC-V Superscalar Microprocessor☆29Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- ☆23Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- Simple runtime for Pulp platforms☆40Updated this week
- RISC-V Nexus Trace TG documentation and reference code☆49Updated last month
- RISC-V Nox core☆62Updated 6 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 9 months ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆51Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆16Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- Chisel Cheatsheet☆32Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 3 months ago
- PCI Express controller model☆48Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- RISC-V Core Local Interrupt Controller (CLINT)☆25Updated last year
- SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...☆26Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 6 months ago