high-performance RTL simulator
☆186Jun 19, 2024Updated last year
Alternatives and similar repositories for essent
Users that are interested in essent are comparing it to the libraries listed below
Sorting:
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Apr 1, 2024Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- ☆52Jan 16, 2025Updated last year
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- ☆19Jan 2, 2026Updated 2 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- WAL enables programmable waveform analysis.☆164Nov 10, 2025Updated 3 months ago
- ☆19Jul 12, 2024Updated last year
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆65Feb 26, 2026Updated last week
- A Rocket-based RISC-V superscalar in-order core☆38Feb 24, 2026Updated last week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- SystemVerilog compiler and language services☆968Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- A dynamic verification library for Chisel.☆160Nov 9, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- ☆67Updated this week
- ☆14Aug 27, 2020Updated 5 years ago
- SystemVerilog synthesis tool☆229Mar 10, 2025Updated 11 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆450Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- design and verification of asynchronous circuits☆43Feb 27, 2026Updated last week
- SystemVerilog to Verilog conversion☆706Nov 24, 2025Updated 3 months ago
- The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming languag…☆472Jan 18, 2026Updated last month
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Nix template for the chisel-based industrial designing flows.☆52Apr 23, 2025Updated 10 months ago
- ☆33Mar 20, 2025Updated 11 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆108Feb 11, 2026Updated 3 weeks ago
- Communication framework for RTL simulation and emulation.☆308Updated this week
- ☆93Updated this week
- SystemVerilog frontend for Yosys☆203Feb 22, 2026Updated last week
- ☆12May 20, 2021Updated 4 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Updated this week
- Circuit IR Compilers and Tools☆2,050Updated this week
- Open-source RTL logic simulator with CUDA acceleration☆257Sep 30, 2025Updated 5 months ago
- End-to-end synthesis and P&R toolchain☆94Updated this week