ucsc-vama / essent

Related projects ⓘ

Alternatives and complementary repositories for essent

• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆140Updated 5 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆107Updated 3 weeks ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆105Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆79Updated 7 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆71Updated 8 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆92Updated 7 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆117Updated 4 months ago
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆61Updated this week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆50Updated this week
• lana555 / dynamatic
  ☆86Updated 8 months ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆148Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆229Updated last week
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆47Updated 4 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆69Updated 4 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆113Updated this week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆176Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆59Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆134Updated 2 weeks ago
• chipsalliance / playground
  chipyard in mill :P
  ☆75Updated 11 months ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆119Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆59Updated 8 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆106Updated this week
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆117Updated last year
• pku-liang / ksim
  ☆36Updated 6 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆44Updated last year
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆145Updated 2 weeks ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆94Updated last year
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆135Updated last year