pulp-platform / aceLinks
☆20Updated last month
Alternatives and similar repositories for ace
Users that are interested in ace are comparing it to the libraries listed below
Sorting:
- ☆33Updated 2 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆20Updated 10 months ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Andes Vector Extension support added to riscv-dv☆18Updated 5 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- RISC-V IOMMU in verilog☆23Updated 3 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Updated 11 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last month
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Updated 7 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- ☆14Updated 11 months ago
- The official NaplesPU hardware code repository☆22Updated 6 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆23Updated 10 months ago
- CORE-V MCU UVM Environment and Test Bench☆25Updated last year
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆11Updated 3 years ago
- ☆31Updated 5 years ago
- DUTH RISC-V Microprocessor☆23Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated last week
- Platform Level Interrupt Controller☆44Updated last year
- ☆29Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year