The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
☆133Jul 11, 2025Updated 11 months ago
Alternatives and similar repositories for cva5
Users that are interested in cva5 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆215Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆271Nov 6, 2024Updated last year
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆114Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆544Updated this week
- Open-source non-blocking L2 cache☆62Updated this week
- CORE-V Family of RISC-V Cores☆355Mar 31, 2026Updated 2 months ago
- RISC-V CPU Core☆434Jun 24, 2025Updated 11 months ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated 4 months ago
- VeeR EH1 core☆949May 29, 2023Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆91Feb 5, 2026Updated 4 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆106May 22, 2026Updated 3 weeks ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆206Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆341Updated this week
- 32-bit Superscalar RISC-V CPU☆1,259Sep 18, 2021Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆811Jun 5, 2026Updated last week
- ☆109May 15, 2026Updated 3 weeks ago
- Simple runtime for Pulp platforms☆52Jun 8, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,243May 29, 2026Updated 2 weeks ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆62Apr 3, 2026Updated 2 months ago
- ☆17Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆613May 26, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆226Jan 11, 2026Updated 5 months ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 3 years ago
- ☆16May 6, 2026Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆294Updated this week
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Common SystemVerilog components☆757Jun 5, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,593Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆524Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- Main Repo for the OpenHW Group Software Task Group☆17Mar 11, 2025Updated last year
- ☆265Dec 22, 2022Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,960Jun 8, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,918Updated this week
- ☆316Jan 23, 2026Updated 4 months ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆275Jun 5, 2026Updated last week