Alternatives and similar repositories for cva5

Users that are interested in cva5 are comparing it to the libraries listed below

• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆126Updated 2 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆106Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆174Updated last month
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆132Updated last week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆169Updated 3 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 5 months ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆68Updated 8 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated last week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 10 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆114Updated this week
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆106Updated 3 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 9 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆59Updated 9 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆186Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 11 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated 2 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆109Updated last month
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated this week