openhwgroup / cva5Links
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
☆109Updated last month
Alternatives and similar repositories for cva5
Users that are interested in cva5 are comparing it to the libraries listed below
Sorting:
- The multi-core cluster of a PULP system.☆104Updated last week
- Generic Register Interface (contains various adapters)☆123Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- RISC-V Verification Interface☆95Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆69Updated last year
- ☆96Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆165Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆169Updated 3 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆121Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆120Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 8 months ago
- RISC-V Nox core☆65Updated 3 months ago
- FuseSoC standard core library☆144Updated last month
- ☆105Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- SystemVerilog synthesis tool☆201Updated 4 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated last month
- A SystemVerilog source file pickler.☆59Updated 8 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- RISC-V System on Chip Template☆158Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆239Updated 8 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago